II CORE BLOCK: BCU (Bus Control Unit)
SDRENA: Enable SDRAM signals (D7) / SDRAM control register (0x39FFC1)
Enable the pins used for the SDRAM.
Write "1": Enabled
Write "0": Disabled
Read: Valid
Writing "1" to SDRENA sets the pins shared with other functions to be used for the SDRAM, with the SDRAM clock output from the BCLK pin. If SDRENA = "0", the shared pins serve other functions.
The SDRAM clock output from the BCLK pin is stopped in the HALT2 and the SLEEP modes.
At cold start, SDRENA is set to "0" (disabled). At hot start, SDRENA retains its status before being initialized.
A1X1MD: Area 1 access speed (D3) / BCLK select register (0x4813A)
Select a number of access cycles for area 1 in x2 speed mode.
Write "1": 2 cycles
Write "0": 4 cycles
Read: Valid
When x2 speed mode is set (#X2SPD pin = "0") and A1X1MD = "1", area 1 is read/written in 2 cycles of the CPU system clock.
When A1X1MD = "0", area 1 is read/written in 4 cycles.
When x1 speed mode is set (#X2SPD pin = "1"), area 1 is always accessed in 2 cycles regardless of the A1X1MD value.
At cold start, A1X1MD is set to "0" (4 cycles). At hot start, A1X1MD retains its status before being initialized.
BCU
S1C33L03 FUNCTION PART | EPSON |