V DMA BLOCK: HSDMA
Trigger Factor
A HSDMA tigger factor can be selected from among 13 types using the HSDMA trigger
HSD0S[3:0]: Ch. 0 trigger
HSD1S[3:0]: Ch. 1 trigger
HSD2S[3:0]: Ch. 2 trigger
HSD3S[3:0]: Ch. 3 trigger
Table 2.2 shows the setting value and the corresponding trigger factor.
Table 2.2 HSDMA Trigger Factor
Value | Ch.0 trigger factor | Ch.1 trigger factor | Ch.2 trigger factor | Ch.3 trigger factor |
0000 | Software trigger | Software trigger | Software trigger | Software trigger |
0001 | K50 port input (falling edge) | K51 port input (falling edge) | K53 port input (falling edge) | K54 port input (falling edge) |
0010 | K50 port input (rising edge) | K51 port input (rising edge) | K53 port input (rising edge) | K54 port input (rising edge) |
0011 | Port 0 input | Port 1 input | Port 2 input | Port 3 input |
0100 | Port 4 input | Port 5 input | Port 6 input | Port 7 input |
0101 | ||||
0110 | ||||
0111 | ||||
1000 | ||||
1001 | ||||
1010 | Serial I/F Ch.0 Rx buffer full | Serial I/F Ch.1 Rx buffer full | Serial I/F Ch.0 Rx buffer full | Serial I/F Ch.1 Rx buffer full |
1011 | Serial I/F Ch.0 Tx buffer empty | Serial I/F Ch.1 Tx buffer empty | Serial I/F Ch.0 Tx buffer empty | Serial I/F Ch.1 Tx buffer empty |
1100 | A/D conversion completion | A/D conversion completion | A/D conversion completion | A/D conversion completion |
By selecting an interrupt factor with the HSDMA trigger
When software trigger is selected, the HSDMA channel can be invoked by writing "1" to the HSTx bit. HST0: Ch. 0 software trigger (D0) / HSDMA software trigger register (0x4029A)
HST1: Ch. 1 software trigger (D1) / HSDMA software trigger register (0x4029A)
HST2: Ch. 2 software trigger (D2) / HSDMA software trigger register (0x4029A)
HST3: Ch. 3 software trigger (D3) / HSDMA software trigger register (0x4029A)
When the selected trigger factor occurs, the trigger flag is set to "1" to invoke the HSDMA channel.
The HSDMA starts a DMA transfer if it has been enabled and the trigger flag is cleared by the hardware at the same time. This makes it possible to queue the HSDMA triggers that have been generated.
The trigger flag can be read and cleared using the HSx_TF bit.
HS0_TF: Ch. 0 trigger flag status/clear (D0) / Ch. 0 trigger flag register (0x4822E)
HS1_TF: Ch. 1 trigger flag status/clear (D0) / Ch. 1 trigger flag register (0x4823E)
HS2_TF: Ch. 2 trigger flag status/clear (D0) / Ch. 2 trigger flag register (0x4824E)
HS3_TF: Ch. 3 trigger flag status/clear (D0) / Ch. 3 trigger flag register (0x4825E)
By writing "1" to this bit, the set trigger flag can be cleared if the DMA transfer has not been started. When this bit is read, "1" indicates that the flag is set and "0" indicates that the flag is cleared.
EPSON | S1C33L03 FUNCTION PART |