Epson S1C33L03 manual 519

VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE

Register name	Address	Bit	Name	Function				Setting				Init.	R/W	Remarks
Areas 14–13	0048122	DF–9	–	reserved					–			–	–	0 when being read.
set-up register	(HW)	D8	A14DRA	Area 14 DRAM selection	1	Used				0	Not used	0	R/W
		D7	A13DRA	Area 13 DRAM selection	1	Used				0	Not used	0	R/W
		D6	A14SZ	Areas 14–13 device size selection	1	8 bits				0	16 bits	0	R/W
		D5	A14DF1	Areas 14–13	A14DF[1:0]				Number of cycles			1	R/W
		D4	A14DF0	output disable delay time	1			1			3.5	1
					1			0			2.5
					0			1			1.5
					0			0			0.5
		D3	–	reserved					–			–	–	0 when being read.
		D2	A14WT2	Areas 14–13 wait control	A14WT[2:0]					Wait cycles		1	R/W
		D1	A14WT1		1		1	1			7	1
		D0	A14WT0		1		1	0			6	1
					1		0	1			5
					1		0	0			4
					0		1	1			3
					0		1	0			2
					0		0	1			1
					0		0	0			0
Areas 8–7	0048128	DF–9	–	reserved					–			–	–	0 when being read.
set-up register	(HW)	D8	A8DRA	Area 8 DRAM selection	1	Used				0	Not used	0	R/W
		D7	A7DRA	Area 7 DRAM selection	1	Used				0	Not used	0	R/W
		D6	A8SZ	Areas 8–7 device size selection	1	8 bits				0	16 bits	0	R/W
		D5	A8DF1	Areas 8–7	A8DF[1:0]				Number of cycles			1	R/W
		D4	A8DF0	output disable delay time	1			1			3.5	1
					1			0			2.5
					0			1			1.5
					0			0			0.5
		D3	–	reserved					–			–	–	0 when being read.
		D2	A8WT2	Areas 8–7 wait control	A8WT[2:0]					Wait cycles		1	R/W
		D1	A8WT1		1		1	1			7	1
		D0	A8WT0		1		1	0			6	1
					1		0	1			5
					1		0	0			4
					0		1	1			3
					0		1	0			2
					0		0	1			1
					0		0	0			0
Areas 6–4	004812A	DF–E	–	reserved					–			–	–	0 when being read.
set-up register	(HW)	DD	A6DF1	Area 6	A6DF[1:0]				Number of cycles			1	R/W
		DC	A6DF0	output disable delay time	1			1			3.5	1
					1			0			2.5
					0			1			1.5
					0			0			0.5
		DB	–	reserved					–			–	–	0 when being read.
		DA	A6WT2	Area 6 wait control	A6WT[2:0]					Wait cycles		1	R/W
		D9	A6WT1		1		1	1			7	1
		D8	A6WT0		1		1	0			6	1
					1		0	1			5
					1		0	0			4
					0		1	1			3
					0		1	0			2
					0		0	1			1
					0		0	0			0
		D7	–	reserved					–			–	–	0 when being read.
		D6	A5SZ	Areas 5–4 device size selection	1	8 bits				0	16 bits	0	R/W
		D5	A5DF1	Areas 5–4	A5DF[1:0]				Number of cycles			1	R/W
		D4	A5DF0	output disable delay time	1			1			3.5	1
					1			0			2.5
					0			1			1.5
					0			0			0.5
		D3	–	reserved								–	–	0 when being read.
		D2	A5WT2	Areas 5–4 wait control	A5WT[2:0]					Wait cycles		1	R/W
		D1	A5WT1		1		1	1			7	1
		D0	A5WT0		1		1	0			6	1
					1		0	1			5
					1		0	0			4
					0		1	1			3
					0		1	0			2
					0		0	1			1
					0		0	0			0

A-1

B-VI

SDRAM

S1C33L03 FUNCTION PART EPSON B-VI-2-23