VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
Register name | Address | Bit | Name | Function |
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| Setting |
| Init. | R/W | Remarks | |||
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Bus control | 004812E | DF | RBCLK | BCLK output control | 1 |
| Fixed at H |
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| 0 | Enabled | 0 | R/W |
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register | (HW) | DE | – | reserved |
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| – |
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| 0 | – | Writing 1 not allowed. | |
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| DD | RBST8 | Burst ROM burst mode selection | 1 |
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| 0 | 0 | R/W |
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| DC | REDO | DRAM page mode selection | 1 |
| EDO |
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| 0 | Fast page | 0 | R/W |
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| DB | RCA1 | Column address size selection | RCA[1:0] |
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| Size | 0 | R/W |
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| DA | RCA0 |
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| 1 |
| 1 |
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| 11 | 0 |
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| 1 |
| 0 |
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| 10 |
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| 0 |
| 1 |
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| 9 |
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| 0 |
| 0 |
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| 8 |
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| D9 | RPC2 | Refresh enable | 1 |
| Enabled |
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| 0 | Disabled | 0 | R/W |
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| D8 | RPC1 | Refresh method selection | 1 |
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| 0 | 0 | R/W |
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| D7 | RPC0 | Refresh RPC delay setup | 1 |
| 2.0 |
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| 0 | 1.0 | 0 | R/W |
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| D6 | RRA1 | Refresh RAS pulse width | RRA[1:0] | Number of cycles | 0 | R/W |
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| D5 | RRA0 | selection |
| 1 |
| 1 |
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| 5 | 0 |
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| 1 |
| 0 |
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| 4 |
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| 0 |
| 1 |
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| 3 |
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| 0 |
| 0 |
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| 2 |
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| D4 | – | reserved |
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| – |
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| 0 | – | Writing 1 not allowed. | |
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| D3 | SBUSST | External interface method selection | 1 |
| #BSL |
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| 0 | A0 | 0 | R/W |
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| D2 | SEMAS | External bus master setup | 1 |
| Existing |
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| 0 | Nonexistent | 0 | R/W |
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| D1 | SEPD | External | 1 |
| Enabled |
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| 0 | Disabled | 0 | R/W |
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| D0 | SWAITE | #WAIT enable | 1 |
| Enabled |
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| 0 | Disabled | 0 | R/W |
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DRAM timing | 0048130 | – | reserved |
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| – |
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| – | – | 0 when being read. | ||
(HW) | DB | A3EEN | Area 3 emulation | 1 |
| Internal ROM |
| 0 | Emulation | 1 | R/W |
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| DA | CEFUNC1 | #CE pin function selection | CEFUNC[1:0] |
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| #CE output | 0 | R/W |
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| D9 | CEFUNC0 |
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| 1 |
| x | #CE7/8..#CE17/18 | 0 |
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| 0 |
| 1 | #CE6..#CE17 |
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| 0 |
| 0 | #CE4..#CE10 |
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| D8 | CRAS | Successive RAS mode setup | 1 |
| Successive |
| 0 | Normal | 0 | R/W |
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| D7 | RPRC1 | DRAM | RPRC[1:0] | Number of cycles | 0 | R/W |
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| D6 | RPRC0 | RAS precharge cycles selection |
| 1 |
| 1 |
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| 4 | 0 |
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| 1 |
| 0 |
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| 3 |
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| 0 |
| 1 |
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| 2 |
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| 0 |
| 0 |
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| 1 |
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| D5 | – | reserved |
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| – |
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| – | – | 0 when being read. | |
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| D4 | CASC1 | DRAM | CASC[1:0] | Number of cycles | 0 | R/W |
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| D3 | CASC0 | CAS cycles selection |
| 1 |
| 1 |
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| 4 | 0 |
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| 1 |
| 0 |
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| 3 |
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| 0 |
| 1 |
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| 2 |
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| 0 |
| 0 |
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| 1 |
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| D2 | – | reserved |
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| – |
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| – | – | 0 when being read. | |
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| D1 | RASC1 | DRAM | RASC[1:0] | Number of cycles | 0 | R/W |
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| D0 | RASC0 | RAS cycles selection |
| 1 |
| 1 |
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| 4 | 0 |
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| 1 |
| 0 |
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| 3 |
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| 0 |
| 1 |
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| 2 |
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| 0 |
| 0 |
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| 1 |
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Access control | 0048132 | DF | A18IO | Area 18, 17 internal/external access | 1 |
| Internal |
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| 0 | External | 0 | R/W |
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register | (HW) | DE | A16IO | Area 16, 15 internal/external access |
|
| access |
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| access | 0 | R/W |
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| DD | A14IO | Area 14, 13 internal/external access |
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| 0 | R/W |
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| DC | A12IO | Area 12, 11 internal/external access |
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| 0 | R/W |
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| DB | – | reserved |
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| – |
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| 0 | – | 0 when being read. | |
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| DA | A8IO | Area 8, 7 internal/external access | 1 |
| Internal |
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| 0 | External | 0 | R/W |
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| D9 | A6IO | Area 6 internal/external access |
|
| access |
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| access | 0 | R/W |
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| D8 | A5IO | Area 5, 4 internal/external access |
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| 0 | R/W |
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| D7 | A18EC | Area 18, 17 endian control | 1 |
| Big endian |
| 0 | Little endian | 0 | R/W |
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| D6 | A16EC | Area 16, 15 endian control |
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| 0 | R/W |
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| D5 | A14EC | Area 14, 13 endian control |
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| 0 | R/W |
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| D4 | A12EC | Area 12, 11 endian control |
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| 0 | R/W |
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| D3 | A10EC | Area 10, 9 endian control |
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| 0 | R/W |
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| D2 | A8EC | Area 8, 7 endian control |
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| 0 | R/W |
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| D1 | A6EC | Area 6 endian control |
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| 0 | R/W |
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| D0 | A5EC | Area 5, 4 endian control |
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| 0 | R/W |
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EPSON | S1C33L03 FUNCTION PART |