III PERIPHERAL BLOCK: SERIAL INTERFACE

1.After setting the #SRDYx signal to a low level (ready to receive), the slave waits for clock input from the master.

2.The master device outputs each bit of data synchronously with the falling edges of the clock. The LSB is output first.

3.This serial interface takes the SIN input into the shift register at the rising edges of the clock that is input from #SCLKx. The data in the shift register is sequentially shifted as bits are taken in. This operation is repeated until the MSB of data is received.

4.When the MSB is taken in, the data in the shift register is transferred to the receive data register, enabling the data to be read out.

•Successive receive operations

When the data received in the shift register is transferred to the receive data register, RDBFx is set to "1" (buffer full), indicating that the received data can be read out.

Since the receive data register can be read out while receiving the next data, data can be received successively. The procedure for receiving is described above.

When RDBFx is set to "1", a receive-data full interrupt factor occurs. Since an interrupt can be generated as set by the interrupt controller, the received data can be read by an interrupt processing routine. In addition, since this interrupt factor can be used to invoke DMA, the received data can be received successively in locations prepared in memory through DMA transfers.

For details on how to control interrupts/DMA, refer to "Serial Interface Interrupts and DMA".

(3)Overrun error

If, during successive receive operation, a receive operation for the next data is completed before the receive data register is read out, the receive data register is overwritten with the new data. Therefore, the receive data register must always be read out before a receive operation for the next data is completed.

When the receive data register is overwritten, an overrun error is generated and the overrun error flag is set to "1".

Ch.0 overrun error flag: OER0 (D2) / Serial I/F Ch.0 status register (0x401E2)

Ch.1 overrun error flag: OER1 (D2) / Serial I/F Ch.1 status register (0x401E7)

Ch.2 overrun error flag: OER2 (D2) / Serial I/F Ch.2 status register (0x401F2)

Ch.3 overrun error flag: OER3 (D2) / Serial I/F Ch.3 status register (0x401F7)

Once the overrun error flag is set to "1", it remains set until it is reset by writing "0" to it in the software. The overrun error is one of the receive-error interrupt factors in the serial interface. An interrupt can be generated for this error by setting the interrupt controller as necessary, so that the error can be processed by an interrupt processing routine.

(4)#SRDYx in slave mode

When receive operations are enabled by writing "1" to RXENx, the #SRDYx signal is turned to a low level, thereby indicating to the master device that the slave is ready to receive. When the LSB of serial data is received, #SRDYx is turned to a high level; when the MSB is received, #SRDYx is returned to a low level, in preparation for the next receive operation.

If an overrun error occurs, #SRDYx is turned to a high level (unable to receive) at that point, with receive operations for the following data thus suspended. In this case, #SRDYx is returned to a low by reading out the data overwritten in the receive data register, and if any receive data follows, the slave restarts receiving data.

(5)Terminating receive operation

Upon completion of a data receive operation, write "0" to the receive-enable bit RXENx to disable receive operations.

A-1

B-III

SIF

S1C33L03 FUNCTION PART

EPSON

B-III-8-11