VII LCD CONTROLLER BLOCK: LCD CONTROLLER
System Settings
Setting the BCU
The control registers of the LCD controller are mapped into
1.A6IO (D9)/access control register (0x48132) = "1"
This sets area 6 so that the internal device will be accessed.
2.A6WT[2:0] (D[A:8])/areas
3.SWAITE (D0)/bus control register (0x4812E) = "1"
This enables the #WAIT signal. This setting is necessary when SDRAM is used.
4.A6EC (D1)/access control register (0x48132) = LCDCEC (D0)/LCDC system control register (0x39FFFD) Make sure the endian formats on the area 6 and LCDC (and SDRAMC) sides match when data is read. In either register, setting the bit to "0" selects little endian (default), and setting the bit to "1" selects big endian.
Display Memory
The LCD controller uses as display memory a necessary amount of memory (maximum of 256K bytes), beginning with the start address of area 7 or 8 (or area 13 or 14 if CEFUNC[1:0] (D[A:9]/0x48130) = "01"). Therefore, SDRAM or SRAM must be included for use as the display memory. The memory configurations and bus settings made using the control registers of the LCD controller are described below.
Selecting the area
Use the VRAMAR (D7)/LCDC system control register (0x39FFFD) to select the area to be used as the display memory.
VRAMAR = "1": Area 8 (CEFUNC = "00") or area 14 (CEFUNC = "01")
VRAMAR = "0": Area 7 (CEFUNC = "00") or area 13 (CEFUNC = "01") (default)
SRAM settings
When using SRAM as the display memory, set the interface method for access from the LCD controller (A0/BSL) and the number of wait cycles to be inserted
LCDCST = "1": BSL method
LCDCST = "0": A0 method (default)
This bit must be set to the same value as in the SBUSST (D3)/bus control register (0x4812E) for the BCU.
Use the VRAMWT[2:0] (D[6:4])/LCDC system control register (0x39FFFD) to select the number of wait cycles. The value set in these three bits
The LCD controller checks the BCU- and
Settings for prioritized use of the bus
The LCD controller reads display data from the display memory via the system bus. Therefore, if the bus is occupied by an external device, the LCD controller cannot update the display. To prevent this problem, the LCD controller can disable DMA requests (#DMAREQx) or bus release requests (#BUSREQ) from outside the chip while it remains enabled (LCDCEN (D5)/LCDC mode register 2 = "1").
LCDC
S1C33L03 FUNCTION PART | EPSON |