4 PERIPHERAL CIRCUITS
Register name | Address | Bit | Name | Function |
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| Setting | Init. | R/W | Remarks | ||||
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0048220 | DF | TC0_L7 | Ch.0 transfer counter[7:0] |
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| X | R/W |
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DMA Ch.0 | (HW) | DE | TC0_L6 | (block transfer mode) |
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| X |
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transfer |
| DD | TC0_L5 |
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| X |
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counter |
| DC | TC0_L4 | Ch.0 transfer counter[15:8] |
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| X |
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register |
| DB | TC0_L3 | (single/successive transfer mode) |
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| X |
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| DA | TC0_L2 |
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| X |
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| D9 | TC0_L1 |
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| X |
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| D8 | TC0_L0 |
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| X |
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| D7 | BLKLEN07 | Ch.0 block length |
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| X | R/W |
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| D6 | BLKLEN06 | (block transfer mode) |
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| X |
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| D5 | BLKLEN05 |
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| X |
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| D4 | BLKLEN04 | Ch.0 transfer counter[7:0] |
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| X |
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| D3 | BLKLEN03 | (single/successive transfer mode) |
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| X |
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| D2 | BLKLEN02 |
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| X |
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| D1 | BLKLEN01 |
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| X |
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| D0 | BLKLEN00 |
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| X |
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0048222 | DF | DUALM0 | Ch.0 address mode selection | 1 |
| Dual addr | 0 |
| Single addr | 0 | R/W |
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DMA Ch.0 | (HW) | DE | D0DIR | D) Invalid |
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| – |
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| – | – |
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control register |
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| S) Ch.0 transfer direction control | 1 |
| Memory WR | 0 |
| Memory RD | 0 | R/W |
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| – | reserved |
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| – |
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| – | – | Undefined in read. | |
Note: |
| D7 | TC0_H7 | Ch.0 transfer counter[15:8] |
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| X | R/W |
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D) Dual address |
| D6 | TC0_H6 | (block transfer mode) |
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| X |
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mode |
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| D5 | TC0_H5 |
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| X |
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S) Single |
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| D4 | TC0_H4 | Ch.0 transfer counter[23:16] |
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| X |
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address |
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| D3 | TC0_H3 | (single/successive transfer mode) |
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| X |
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mode |
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| D2 | TC0_H2 |
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| X |
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| D1 | TC0_H1 |
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| X |
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| D0 | TC0_H0 |
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| X |
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0048224 | DF | S0ADRL15 | D) Ch.0 source address[15:0] |
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| X | R/W |
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DMA Ch.0 | (HW) | DE | S0ADRL14 | S) Ch.0 memory address[15:0] |
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| X |
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| DD | S0ADRL13 |
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| X |
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source address |
| DC | S0ADRL12 |
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| X |
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| DB | S0ADRL11 |
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| X |
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| DA | S0ADRL10 |
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| X |
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Note: |
| D9 | S0ADRL9 |
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| X |
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D) Dual address |
| D8 | S0ADRL8 |
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| X |
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mode |
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| D7 | S0ADRL7 |
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| X |
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S) Single |
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| D6 | S0ADRL6 |
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| X |
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address |
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| D5 | S0ADRL5 |
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| X |
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mode |
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| D4 | S0ADRL4 |
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| X |
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| D3 | S0ADRL3 |
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| X |
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| D2 | S0ADRL2 |
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| X |
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| D1 | S0ADRL1 |
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| X |
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| D0 | S0ADRL0 |
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| X |
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0048226 | DF | – | reserved |
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| – |
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| – | – |
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DMA Ch.0 | (HW) | DE | DATSIZE0 | Ch.0 transfer data size | 1 |
| Half word | 0 |
| Byte | 0 | R/W |
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| DD | S0IN1 | D) Ch.0 source address control | S0IN[1:0] |
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| Inc/dec | 0 | R/W |
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source address |
| DC | S0IN0 | S) Ch.0 memory address control |
| 1 | 1 |
| Inc.(no init) | 0 |
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| 1 | 0 |
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| Inc.(init) |
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| 0 | 1 |
| Dec.(no init) |
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Note: |
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| 0 | 0 |
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| Fixed |
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D) Dual address |
| DB | S0ADRH11 | D) Ch.0 source address[27:16] |
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| X | R/W |
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mode |
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| DA | S0ADRH10 | S) Ch.0 memory address[27:16] |
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| X |
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S) Single |
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| D9 | S0ADRH9 |
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| X |
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address |
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| D8 | S0ADRH8 |
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| X |
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mode |
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| D7 | S0ADRH7 |
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| X |
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| D6 | S0ADRH6 |
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| X |
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| D5 | S0ADRH5 |
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| X |
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| D4 | S0ADRH4 |
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| X |
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| D3 | S0ADRH3 |
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| X |
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| D2 | S0ADRH2 |
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| X |
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| D1 | S0ADRH1 |
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| X |
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| D0 | S0ADRH0 |
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| X |
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S1C33L03 PRODUCT PART | EPSON |