III PERIPHERAL BLOCK: SERIAL INTERFACE
Outline of
In the
Master and slave modes
Either the
In this mode,
The synchronizing clock is output from the #SCLKx pin, enabling an external (slave side) serial input/output device to be controlled. The #SRDYx pin is also used to input a signal that indicates whether the external serial input/output device is ready to transmit or receive (when ready in a low level).
In this mode,
The synchronizing clock is input from the #SCLKx pin for use as the synchronizing clock of the serial interface. In addition, a #SRDYx signal indicating whether the serial interface is ready to transmit or receive (when ready in a low level) is output from the #SRDYx pin.
Figure 8.2 shows an example of how the input/output pins are connected in the
S1C33 |
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| serial device |
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| serial device |
SINx |
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| Data input |
| SINx |
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| Data input |
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SOUTx |
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| Data output |
| SOUTx |
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| Data output |
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#SCLKx |
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| Clock input |
| #SCLKx |
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| Clock output |
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#SRDYx |
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| Ready output |
| #SRDYx |
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| Ready input |
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| (1) Master mode |
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| (2) Slave mode |
Figure 8.2 Example of Connection in
In
Data length: 8 bits
Start bit: None
Stop bit: None
Parity bit: None
#SCLKx |
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| LSB | MSB |
Data | D0 D1 D2 D3 D4 D5 D6 D7 |
Figure 8.3
Serial data is transmitted and received starting with the LSB.
EPSON | S1C33L03 FUNCTION PART |