III PERIPHERAL BLOCK: WATCHDOG TIMER
Resetting the watchdog timer
When using the watchdog timer, prepare a routine to reset the
The
If the watchdog timer is not reset within the set interval for any reason, the CPU is made to enter trap processing by an NMI and starts executing the processing routine indicated by the NMI vector.
The NMI trap vector address is set to 0x0C0001C by default.
The trap table base address can be changed using the TTBR registers (0x48134 to 0x48137).
Operation in Standby Modes
During HALT mode
In HALT mode (basic mode or HALT2 mode), the prescaler and watchdog timer are operating. Consequently, if HALT mode continues beyond the NMI generation interval, HALT mode is cleared by the NMI.
To disable the watchdog timer in HALT mode, set EWD to "0" before executing the halt instruction or turn off the
If the NMI is disabled by EWD, the
If HALT mode was entered after the
During SLEEP mode
In SLEEP mode, the prescaler is turned off. Therefore, the watchdog timer also stops operating. To prevent generation of an unwanted NMI after clearing SLEEP mode, reset the
EPSON | S1C33L03 FUNCTION PART |