VII LCD CONTROLLER BLOCK: LCD CONTROLLER
Controlling the GPIO Pins
The pins described below can be used as
The FPDAT[3:0] signal output pins can be used as
Table 2.19 GOP Control Bits
Pin name | GPO signal name | Output control bit |
FPDAT0 | GPO3 | GPO3D (D3)/GPIO status/control register(0x39FFF9) |
FPDAT1 | GPO4 | GPO4D (D4)/GPIO status/control register(0x39FFF9) |
FPDAT2 | GPO5 | GPO5D (D5)/GPIO status/control register(0x39FFF9) |
FPDAT3 | GPO6 | GPO6D (D6)/GPIO status/control register(0x39FFF9) |
Setting the GPOxD bit to 1 drives the GPOx output high, and setting the GPOxD bit to 0 drives the GPOx output low.
Note: In
While the LCD controller is enabled (LCDCEN (D5)/LCDC mode register 2 = "1"), bus release requests (#BUSREQ) from outside the chip can be disabled. When the BREQEN (D2)/LCDC system control register (0x39FFFD) is set to "0" (default), bus release requests from outside will no longer be accepted while LCDCEN = "1". As a result, the pins listed below will not be used for
Table 2.20 GPIO Control Bits
Pin name | GPIO signal | I/O control bit | I/O data | |
name | ||||
|
|
| ||
#BUSREQ/P34 | GPIO0 | GPIO0C (D0)/GPIO configuration | GPIO0D (D0)/GPIO status/control | |
|
| register(0x39FFF8) | register(0x39FFF9) | |
#BUSACK/P35 | GPIO1 | GPIO1C (D1)/GPIO configuration | GPIO1D (D1)/GPIO status/control | |
|
| register(0x39FFF8) | register(0x39FFF9) | |
#BUSGET/P31 | GPIO2 | GPIO2C (D2)/GPIO configuration | GPIO2D (D2)/GPIO status/control | |
|
| register(0x39FFF8) | register(0x39FFF9) |
Set the GPIOxC bits to "0" (default) when the GPIOx pins are used as input ports, or "1" when the GPIOx pins are used as output ports.
When the pins are set for input, it possible to determine their
EPSON | S1C33L03 FUNCTION PART |