III PERIPHERAL BLOCK: PRESCALER
I/O Memory of Prescaler
Table 2.3 shows the control bits of the prescaler.
Table 2.3 Control Bits of Prescaler
Register name | Address | Bit | Name | Function |
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| Setting | Init. | R/W | Remarks | |||
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|
0040140 | – | reserved |
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| – |
| – | – | 0 when being read. | |||
clock select | (B) | D1 | P8TPCK5 | 1 | θ/1 |
|
| 0 | Divided clk. | 0 | R/W | θ: selected by | ||
register |
| D0 | P8TPCK4 | 1 | θ/1 |
|
| 0 | Divided clk. | 0 | R/W | Prescaler clock select | ||
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| register (0x40181) |
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0040145 | D7 | P8TON5 | 1 | On |
|
| 0 | Off | 0 | R/W |
| |||
clock control | (B) | D6 | P8TS52 | 1 |
| 1 | 1 |
|
| θ/256 | 0 | R/W | θ: selected by | |
register |
| D5 | P8TS51 | clock division ratio selection | 1 |
| 1 | 0 |
|
| θ/128 | 0 | R/W | Prescaler clock select |
|
| D4 | P8TS50 |
| 1 |
| 0 | 1 |
|
| θ/64 | 0 | R/W | register (0x40181) |
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|
|
| 1 |
| 0 | 0 |
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| θ/32 |
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| 0 |
| 1 | 1 |
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| θ/16 |
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| |
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| 0 |
| 1 | 0 |
|
| θ/8 |
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| generate the clock for |
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|
| 0 |
| 0 | 1 |
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| θ/4 |
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| the serial I/F Ch.3. |
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| 0 |
| 0 | 0 |
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| θ/2 |
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| D3 | P8TON4 | 1 | On |
|
| 0 | Off | 0 | R/W |
| ||
|
| D2 | P8TS42 | 1 |
| 1 | 1 |
|
| θ/4096 | 0 | R/W | θ: selected by | |
|
| D1 | P8TS41 | clock division ratio selection | 1 |
| 1 | 0 |
|
| θ/2048 | 0 | R/W | Prescaler clock select |
|
| D0 | P8TS40 |
| 1 |
| 0 | 1 |
|
| θ/64 | 0 | R/W | register (0x40181) |
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| 1 |
| 0 | 0 |
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| θ/32 |
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| 0 |
| 1 | 1 |
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| θ/16 |
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| |
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| 0 |
| 1 | 0 |
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| θ/8 |
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| generate the clock for |
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| 0 |
| 0 | 1 |
|
| θ/4 |
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| the serial I/F Ch.2. |
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| 0 |
| 0 | 0 |
|
| θ/2 |
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|
0040146 | – | reserved |
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|
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| – |
| – | – | 0 when being read. | |||
clock select | (B) | D3 | P8TPCK3 | 1 | θ/1 |
|
| 0 | Divided clk. | 0 | R/W | θ: selected by | ||
register |
| D2 | P8TPCK2 | 1 | θ/1 |
|
| 0 | Divided clk. | 0 | R/W | Prescaler clock select | ||
|
| D1 | P8TPCK1 | 1 | θ/1 |
|
| 0 | Divided clk. | 0 | R/W | register (0x40181) | ||
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| D0 | P8TPCK0 | 1 | θ/1 |
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| 0 | Divided clk. | 0 | R/W |
| ||
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| |
0040147 | – | reserved |
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|
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| – |
| – | – | 0 when being read. | |||
clock control | (B) | D3 | P16TON0 | 1 | On |
|
| 0 | Off | 0 | R/W |
| ||
register |
| D2 | P16TS02 | P16TS0[2:0] |
| Division ratio | 0 | R/W | θ: selected by | |||||
|
| D1 | P16TS01 | clock division ratio selection | 1 |
| 1 | 1 |
|
| θ/4096 | 0 |
| Prescaler clock select |
|
| D0 | P16TS00 |
| 1 |
| 1 | 0 |
|
| θ/1024 | 0 |
| register (0x40181) |
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|
|
| 1 |
| 0 | 1 |
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| θ/256 |
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| 1 |
| 0 | 0 |
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| θ/64 |
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| |
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| 0 |
| 1 | 1 |
|
| θ/16 |
|
| used as a watchdog |
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|
| 0 |
| 1 | 0 |
|
| θ/4 |
|
| timer. |
|
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|
|
| 0 |
| 0 | 1 |
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| θ/2 |
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| 0 |
| 0 | 0 |
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| θ/1 |
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| |
0040148 | – | reserved |
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|
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| – |
| – | – | 0 when being read. | |||
clock control | (B) | D3 | P16TON1 | 1 | On |
|
| 0 | Off | 0 | R/W |
| ||
register |
| D2 | P16TS12 | P16TS1[2:0] |
| Division ratio | 0 | R/W | θ: selected by | |||||
|
| D1 | P16TS11 | clock division ratio selection | 1 |
| 1 | 1 |
|
| θ/4096 | 0 |
| Prescaler clock select |
|
| D0 | P16TS10 |
| 1 |
| 1 | 0 |
|
| θ/1024 | 0 |
| register (0x40181) |
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|
|
| 1 |
| 0 | 1 |
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| θ/256 |
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| 1 |
| 0 | 0 |
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| θ/64 |
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| 0 |
| 1 | 1 |
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| θ/16 |
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| 0 |
| 1 | 0 |
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| θ/4 |
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| 0 |
| 0 | 1 |
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| θ/2 |
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| 0 |
| 0 | 0 |
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| θ/1 |
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| |
0040149 | – | reserved |
|
|
|
| – |
| – | – | 0 when being read. | |||
clock control | (B) | D3 | P16TON2 | 1 | On |
|
| 0 | Off | 0 | R/W |
| ||
register |
| D2 | P16TS22 | P16TS2[2:0] |
| Division ratio | 0 | R/W | θ: selected by | |||||
|
| D1 | P16TS21 | clock division ratio selection | 1 |
| 1 | 1 |
|
| θ/4096 | 0 |
| Prescaler clock select |
|
| D0 | P16TS20 |
| 1 |
| 1 | 0 |
|
| θ/1024 | 0 |
| register (0x40181) |
|
|
|
|
| 1 |
| 0 | 1 |
|
| θ/256 |
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|
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| 1 |
| 0 | 0 |
|
| θ/64 |
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| 0 |
| 1 | 1 |
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| θ/16 |
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| 0 |
| 1 | 0 |
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| θ/4 |
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| 0 |
| 0 | 1 |
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| θ/2 |
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| 0 |
| 0 | 0 |
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| θ/1 |
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PSC
S1C33L03 FUNCTION PART | EPSON |