1 OUTLINE
1.2 Block Diagram
VDD
VSS |
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| S1C33L03 | |
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VDDE |
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A[23:0] |
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D[15:0] |
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| S1C33000 | ||
#RD |
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#WRL/#WR/#WE |
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#WRH/#BSH |
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#HCAS, #LCAS, #RAS[1:0] |
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| CPU Core |
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#CE10EX, #CE[9:3] |
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#EMEMRD |
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#WAIT(P30) |
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| Bus Control Unit |
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#DRD(P20), #DWE/#SDWE(P21) |
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#GAAS(P21), #GARD(P31) |
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#SDCE[1:0] |
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| SDRAM Controller |
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#SDCAS, #SDRAS |
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SDA10, SDCKE, HDQM, LDQM |
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#RESET
#NMI
#X2SPD
ICEMD
DSIO
EA10MD[1:0]
BCLK
#BUSREQ(P34)
#BUSACK(P35)
#BUSGET(P31)
DPCO(P13) DCLK(P14)
OSC3 |
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OSC4 |
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| OSC3/PLL | |
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PLLS[1:0] |
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PLLC |
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| Prescaler | |
OSC1 |
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OSC2 |
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| OSC1 | |
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FOSC1(P14) |
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| Clock | |
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| Timer | |
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| Intelligent | |
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| DMA (128 ch.) | |
#DMAREQx(K50, K51, K53, K54) |
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#DMAACKx(P32, P33, P04, P06) |
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| DMA (4 ch.) | ||
#DMAENDx(P15, P16, P05, P07) |
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| RAM | |
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| 8KB | |
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| I/O Port | ||
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Interrupt
Controller
Programmable
Timer (6 ch.)
Programmable
Timer (6 ch.)
Serial Interface
(4 ch.)
A/D Converter
(8 ch.)
LCD Controller
Input Port
SINx(P00, P04, P27, P33)
SOUTx(P01, P05, P26, P16)
#SCLKx(P02, P06, P25, P15)
#SRDYx(P03, P07, P24, P32)
AVDDE
FPDAT[7:4]
FPDAT[3:0]/GPO[6:3]
FPFRAME
FPLINE
FPSHIFT
DRDY(MOD/FPSHIFT2)
LCDPWR
Figure 1.2.1 S1C33L03 Block Diagram
S1C33L03 PRODUCT PART | EPSON |