III PERIPHERAL BLOCK: SERIAL INTERFACE

•Ch.2 and Ch.3

For Ch.2 and Ch.3, either port input interrupts or 16-bit timer interrupts are selected, and HSDMA is invoked by means of those interrupt factor (See Table 8.10).

When port input interrupts are selected, Serial I/F Ch.2 receive buffer full corresponds to port 1, and transmit buffer empty to port 3. Therefore, HSDMA can be invoked by setting HSDMA Ch.1 and Ch.3 trigger factor values (D[7:4]/0x40298, D[7:4]/0x40299) of "0011".

Similarly, as Serial I/F Ch.3 receive buffer full corresponds to port 4, and transmit buffer empty to port 6, HSDMA can be invoked by setting HSDMA Ch.0 and Ch.2 trigger factor values (D[7:4]/0x40298, D[7:4]/0x40299) of "0100".

When 16-bit timer interrupts are selected, the HSDMA trigger factor set values are different for receive buffer full and transmit buffer empty.

In the case of Serial I/F Ch.2, receive buffer full corresponds to 16-bit timer 5 compare B, and transmit buffer empty to 16-bit timer 5 compare A. Therefore, to use HSDMA for both transmission and reception, an HSDMA Ch.3trigger factor value (D[7:4]/0x40299) of "1001" must be set when the Ch.1 trigger factor value (D[7:4]/0x40298) has been set to "1000". (HSDMA can also be invoked by the reverse combination of set values.)

Similarly, to use 16-bit timer 4 compare A and B on Serial I/F Ch.3, HSDMA can be invoked by setting an HSDMA Ch.2 value of "1001" when the Ch.0 value has been set to "1000". (HSDMA can also be invoked by the reverse combination of set values.)

With interrupts other than receive buffer full and transmit buffer empty, also, the above approach can be used to activate the HSDMA channel set for the corresponding port No. or 16-bit timer compare.

Trap vectors

•Ch.0 and Ch.1

The trap-vector address of each default interrupt factor is set as follows:

Ch.0 receive-error interrupt:

0x0C000E0

Ch.0 receive-buffer full interrupt:

0x0C000E4

Ch.0 transmit-buffer empty interrupt:

0x0C000E8

Ch.1 receive-error interrupt:

0x0C000EC

Ch.1 receive-buffer full interrupt:

0x0C000F0

Ch.1 transmit-buffer empty interrupt:

0x0C000F4

The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).

•Ch.2 and Ch.3

Ch.2 and Ch.3 do not have dedicated interrupt signals. Either a port input interrupt or 16-bit timer interrupt is selected, and interrupt handling is performed accordingly.

For details, refer to the "Trap Vector" subsection in the "16-Bit Programmable Timers" or "Input/Output Ports" section.

A-1

B-III

SIF

S1C33L03 FUNCTION PART

EPSON

B-III-8-27