II CORE BLOCK: BCU (Bus Control Unit)
Register name | Address | Bit | Name | Function |
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| Setting |
| Init. | R/W | Remarks | |||
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DRAM timing | 0048130 | – | reserved |
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| – |
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| – | – | 0 when being read. | ||
(HW) | DB | A3EEN | Area 3 emulation | 1 |
| Internal ROM |
| 0 | Emulation | 1 | R/W |
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| DA | CEFUNC1 | #CE pin function selection | CEFUNC[1:0] |
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| #CE output | 0 | R/W |
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| D9 | CEFUNC0 |
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| 1 | x | #CE7/8..#CE17/18 | 0 |
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| 0 | 1 | #CE6..#CE17 |
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| 0 | 0 | #CE4..#CE10 |
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| D8 | CRAS | Successive RAS mode setup | 1 |
| Successive |
| 0 | Normal | 0 | R/W |
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| D7 | RPRC1 | DRAM | RPRC[1:0] | Number of cycles | 0 | R/W |
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| D6 | RPRC0 | RAS precharge cycles selection |
| 1 | 1 |
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| 4 | 0 |
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| 1 | 0 |
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| 3 |
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| 0 | 1 |
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| 2 |
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| 0 | 0 |
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| 1 |
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| D5 | – | reserved |
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| – |
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| – | – | 0 when being read. | |
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| D4 | CASC1 | DRAM | CASC[1:0] | Number of cycles | 0 | R/W |
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| D3 | CASC0 | CAS cycles selection |
| 1 | 1 |
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| 4 | 0 |
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| 1 | 0 |
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| 3 |
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| 0 | 1 |
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| 2 |
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| 0 | 0 |
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| 1 |
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| D2 | – | reserved |
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| – |
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| – | – | 0 when being read. | |
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| D1 | RASC1 | DRAM | RASC[1:0] | Number of cycles | 0 | R/W |
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| D0 | RASC0 | RAS cycles selection |
| 1 | 1 |
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| 4 | 0 |
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| 1 | 0 |
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| 3 |
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| 0 | 1 |
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| 2 |
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| 0 | 0 |
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| 1 |
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Access control | 0048132 | DF | A18IO | Area 18, 17 internal/external access | 1 |
| Internal |
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| 0 | External | 0 | R/W |
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register | (HW) | DE | A16IO | Area 16, 15 internal/external access |
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| access |
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| access | 0 | R/W |
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| DD | A14IO | Area 14, 13 internal/external access |
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| 0 | R/W |
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| DC | A12IO | Area 12, 11 internal/external access |
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| 0 | R/W |
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| DB | – | reserved |
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| – |
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| 0 | – | 0 when being read. | |
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| DA | A8IO | Area 8, 7 internal/external access | 1 |
| Internal |
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| 0 | External | 0 | R/W |
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| D9 | A6IO | Area 6 internal/external access |
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| access |
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| access | 0 | R/W |
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| D8 | A5IO | Area 5, 4 internal/external access |
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| 0 | R/W |
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| D7 | A18EC | Area 18, 17 endian control | 1 |
| Big endian |
| 0 | Little endian | 0 | R/W |
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| D6 | A16EC | Area 16, 15 endian control |
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| 0 | R/W |
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| D5 | A14EC | Area 14, 13 endian control |
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| 0 | R/W |
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| D4 | A12EC | Area 12, 11 endian control |
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| 0 | R/W |
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| D3 | A10EC | Area 10, 9 endian control |
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| 0 | R/W |
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| D2 | A8EC | Area 8, 7 endian control |
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| 0 | R/W |
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| D1 | A6EC | Area 6 endian control |
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| 0 | R/W |
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| D0 | A5EC | Area 5, 4 endian control |
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| 0 | R/W |
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G/A read signal | 0048138 | DF | A18AS | Area 18, 17 address strobe signal | 1 |
| Enabled |
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| 0 | Disabled | 0 | R/W |
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control register | (HW) | DE | A16AS | Area 16, 15 address strobe signal |
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| 0 | R/W |
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| DD | A14AS | Area 14, 13 address strobe signal |
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| 0 | R/W |
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| DC | A12AS | Area 12, 11 address strobe signal |
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| 0 | R/W |
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| DB | – | reserved |
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| – |
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| 0 | – | 0 when being read. | |
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| DA | A8AS | Area 8, 7 address strobe signal | 1 |
| Enabled |
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| 0 | Disabled | 0 | R/W |
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| D9 | A6AS | Area 6 address strobe signal |
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| 0 | R/W |
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| D8 | A5AS | Area 5, 4 address strobe signal |
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| 0 | R/W |
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| D7 | A18RD | Area 18, 17 read signal | 1 |
| Enabled |
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| 0 | Disabled | 0 | R/W |
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| D6 | A16RD | Area 16, 15 read signal |
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| 0 | R/W |
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| D5 | A14RD | Area 14, 13 read signal |
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| 0 | R/W |
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| D4 | A12RD | Area 12, 11 read signal |
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| 0 | R/W |
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| D3 | – | reserved |
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| – |
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| 0 | – | 0 when being read. | |
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| D2 | A8RD | Area 8, 7 read signal | 1 |
| Enabled |
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| 0 | Disabled | 0 | R/W |
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| D1 | A6RD | Area 6 read signal |
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| 0 | R/W |
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| D0 | A5RD | Area 5, 4 read signal |
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| 0 | R/W |
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BCLK select | 004813A | – | reserved |
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| – |
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| 0 | – | 0 when being read. | ||
register | (B) | D3 | A1X1MD | Area 1 | 1 |
| 2 cycles |
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| 0 | 4 cycles | 0 | R/W | x2 speed mode only | |
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| D2 | – | reserved |
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| – |
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| 0 | – | 0 when being read. | |
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| D1 | BCLKSEL1 | BCLK output clock selection | BCLKSEL[1:0] |
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| BCLK | 0 | R/W |
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| D0 | BCLKSEL0 |
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| 1 | 1 |
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| PLL_CLK | 0 |
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| 1 | 0 |
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| OSC3_CLK |
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| 0 | 1 |
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| BCU_CLK |
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| 0 | 0 |
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| CPU_CLK |
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BCU
S1C33L03 FUNCTION PART | EPSON |