APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS

A-1

A.5 SRAM (70ns)

SRAM interface setup examples – 70ns

Operating

Read cycle

Output disable

 

 

 

Write cycle

frequency

Wait cycle

Read cycle

delay cycle

20MHz

2

3

3

1.5

25MHz

2

3

3

1.5

33MHz

3

4

4

1.5

SRAM interface timing – 70ns

SRAM interface

 

 

 

33MHz

25MHz

20MHz

 

Parameter

Symbol

Min.

Max.

Cycle

Time

Cycle

Time

Cycle

Time

A-ap

<Read cycle>

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read cycle time

tRC

70

–

4

120

3

120

3

150

 

Address access time

tACC

–

70

4

120

3

120

3

150

 

#CE access time

tACS

–

70

4

120

3

120

3

150

 

#OE access time

tOE

–

40

3.5

105

2.5

100

2.5

125

 

Output disable delay time

tOHZ

0

30

1.5

45

1.5

60

1.5

75

 

<Write cycle>

 

 

 

 

 

 

 

 

 

 

Write cycle time

tWC

70

–

4

120

3

120

3

150

 

Address enable time

tAW

60

–

3.5

105

2.5

100

2.5

125

 

Write pulse width

tWP

55

–

3

90

2

80

2

100

 

Input data setup time

tDW

30

–

3

90

2

80

2

100

 

Input data hold time

tDH

0

–

0.5

15

0.5

20

0.5

25

 

SRAM: 70ns, CPU: 33MHz, read cycle

BCLK

tRC

A[23:0]

tACC

#CEx

tACS

#RD

tOE

 

 

 

tOHZ

 

 

RD data

D[15:0]

SRAM: 70ns, CPU: 33MHz, write cycle

BCLK

tWC

A[23:0]

tAW

#CEx

tWP

#WR

tDW tDH

D[15:0]

WR data

S1C33L03 PRODUCT PART

EPSON

A-125