II CORE BLOCK: INTRODUCTION
II-1 INTRODUCTION
The core block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC (Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and an SBUS (Internal Silicon Integration Bus) for interfacing with
C33 Internal Memory Block
Internal RAM
(Area 0)
Internal ROM
(Area 10)
C33 DMA Block | C33 SDRAM Controller Block | C33 LCD Controller Block | ||||||||
C33_DMA |
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| C33_CORE |
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| CORE |
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| Intro |
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| C33_SBUS |
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| C33 Core Block |
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| C33_ADC |
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| C33_PERI |
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(A/D converter) |
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| Clock timer, Serial interface, Ports) |
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| C33 Analog Block |
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| C33 Peripheral Block |
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Figure 1.1 Core Block
Note: Internal ROM is not provided in the S1C33L03.
S1C33L03 FUNCTION PART | EPSON |