II CORE BLOCK: INTRODUCTION

A-1

II-1 INTRODUCTION

The core block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC (Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and an SBUS (Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells.

C33 Internal Memory Block

Internal RAM

(Area 0)

Internal ROM

(Area 10)

C33 DMA Block

C33 SDRAM Controller Block

C33 LCD Controller Block

C33_DMA

 

 

C33_SDRAMC

 

 

C33_LCDC

 

(IDMA, HSDMA)

 

 

(SDRAM interface)

 

 

 

(LCD panel interface)

 

 

Pads

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C33_CORE

 

 

PAD

 

 

 

 

 

 

 

 

 

 

 

 

_

 

Pads

 

 

 

 

 

 

 

 

 

CORE

 

 

 

 

 

(CPU, BCU, ITC, CLG, DBG)

 

 

 

 

B-II

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Intro

 

 

 

 

 

C33_SBUS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C33 Core Block

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C33_ADC

 

 

C33_PERI

 

 

PAD

 

 

 

 

 

 

 

 

 

 

 

 

(A/D converter)

 

(Prescaler, 8-bit timer, 16-bit timer,

PERI

 

Pads

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock timer, Serial interface, Ports)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C33 Analog Block

 

 

C33 Peripheral Block

 

 

Figure 1.1 Core Block

Note: Internal ROM is not provided in the S1C33L03.

S1C33L03 FUNCTION PART

EPSON

B-II-1-1