III PERIPHERAL BLOCK: SERIAL INTERFACE
Register name | Address | Bit | Name | Function |
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| Setting | Init. | R/W | Remarks | |||||
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Serial I/F Ch.1 | 00401E7 | – | – |
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| – |
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| – | – | 0 when being read. | ||
status register | (B) | D5 | TEND1 | Ch.1 | 1 |
| Transmitting |
| 0 |
| End | 0 | R |
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| D4 | FER1 | Ch.1 flaming error flag | 1 |
| Error |
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| 0 |
| Normal | 0 | R/W | Reset by writing 0. | |
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| D3 | PER1 | Ch.1 parity error flag | 1 |
| Error |
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| 0 |
| Normal | 0 | R/W | Reset by writing 0. | |
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| D2 | OER1 | Ch.1 overrun error flag | 1 |
| Error |
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| 0 |
| Normal | 0 | R/W | Reset by writing 0. | |
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| D1 | TDBE1 | Ch.1 transmit data buffer empty | 1 |
| Empty |
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| 0 |
| Buffer full | 1 | R |
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| D0 | RDBF1 | Ch.1 receive data buffer full | 1 |
| Buffer full |
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| 0 |
| Empty | 0 | R |
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Serial I/F Ch.1 | 00401E8 | D7 | TXEN1 | Ch.1 transmit enable | 1 |
| Enabled |
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| 0 |
| Disabled | 0 | R/W |
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control register | (B) | D6 | RXEN1 | Ch.1 receive enable | 1 |
| Enabled |
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| 0 |
| Disabled | 0 | R/W |
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| D5 | EPR1 | Ch.1 parity enable | 1 |
| With parity |
| 0 |
| No parity | X | R/W | Valid only in | |||
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| D4 | PMD1 | Ch.1 parity mode selection | 1 |
| Odd |
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| 0 |
| Even | X | R/W | asynchronous mode. | |
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| D3 | STPB1 | Ch.1 stop bit selection | 1 |
| 2 bits |
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| 0 |
| 1 bit | X | R/W |
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| D2 | SSCK1 | Ch.1 input clock selection | 1 |
| #SCLK1 |
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| 0 |
| Internal clock | X | R/W |
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| D1 | SMD11 | Ch.1 transfer mode selection | SMD1[1:0] |
| Transfer mode | X | R/W |
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| D0 | SMD10 |
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| 1 |
| 1 | X |
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| 1 |
| 0 |
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| 0 |
| 1 | Clock sync. Slave |
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| 0 |
| 0 | Clock sync. Master |
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Serial I/F Ch.1 | 00401E9 | – | – |
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| – |
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| – | – | 0 when being read. | ||
IrDA register | (B) | D4 | DIVMD1 | Ch.1 async. clock division ratio | 1 |
| 1/8 |
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| 0 |
| 1/16 | X | R/W |
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| D3 | IRTL1 | Ch.1 IrDA I/F output logic inversion | 1 |
| Inverted |
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| 0 |
| Direct | X | R/W | Valid only in | ||
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| D2 | IRRL1 | Ch.1 IrDA I/F input logic inversion | 1 |
| Inverted |
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| 0 |
| Direct | X | R/W | asynchronous mode. | ||
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| D1 | IRMD11 | Ch.1 interface mode selection | IRMD1[1:0] |
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| I/F mode | X | R/W |
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| D0 | IRMD10 |
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| 1 |
| 1 |
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| reserved | X |
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| 1 |
| 0 |
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| IrDA 1.0 |
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| 0 |
| 1 |
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| reserved |
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| 0 |
| 0 |
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| General I/F |
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Serial I/F Ch.2 | 00401F0 | D7 | TXD27 | Serial I/F Ch.2 transmit data |
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| 0x0 to 0xFF(0x7F) | X | R/W |
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transmit data | (B) | D6 | TXD26 | TXD27(26) = MSB |
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| X |
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register |
| D5 | TXD25 | TXD20 = LSB |
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| X |
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| D4 | TXD24 |
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| X |
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| D3 | TXD23 |
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| X |
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| D2 | TXD22 |
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| X |
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| D1 | TXD21 |
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| X |
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| D0 | TXD20 |
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| X |
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Serial I/F Ch.2 | 00401F1 | D7 | RXD27 | Serial I/F Ch.2 receive data |
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| 0x0 to 0xFF(0x7F) | X | R |
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receive data | (B) | D6 | RXD26 | RXD27(26) = MSB |
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| X |
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register |
| D5 | RXD25 | RXD20 = LSB |
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| X |
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| D4 | RXD24 |
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| X |
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| D3 | RXD23 |
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| X |
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| D2 | RXD22 |
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| X |
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| D1 | RXD21 |
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| X |
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| D0 | RXD20 |
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| X |
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Serial I/F Ch.2 | 00401F2 | – | reserved |
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| – |
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| – | – | 0 when being read. | ||
status register | (B) | D5 | TEND2 | Ch.2 | 1 |
| Transmitting |
| 0 |
| End | 0 | R |
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| D4 | FER2 | Ch.2 flaming error flag | 1 |
| Error |
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| 0 |
| Normal | 0 | R/W | Reset by writing 0. | |
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| D3 | PER2 | Ch.2 parity error flag | 1 |
| Error |
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| 0 |
| Normal | 0 | R/W | Reset by writing 0. | |
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| D2 | OER2 | Ch.2 overrun error flag | 1 |
| Error |
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| 0 |
| Normal | 0 | R/W | Reset by writing 0. | |
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| D1 | TDBE2 | Ch.2 transmit data buffer empty | 1 |
| Empty |
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| 0 |
| Buffer full | 1 | R |
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| D0 | RDBF2 | Ch.2 receive data buffer full | 1 |
| Buffer full |
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| 0 |
| Empty | 0 | R |
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Serial I/F Ch.2 | 00401F3 | D7 | TXEN2 | Ch.2 transmit enable | 1 |
| Enabled |
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| 0 |
| Disabled | 0 | R/W |
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control register | (B) | D6 | RXEN2 | Ch.2 receive enable | 1 |
| Enabled |
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| 0 |
| Disabled | 0 | R/W |
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| D5 | EPR2 | Ch.2 parity enable | 1 |
| With parity |
| 0 |
| No parity | X | R/W | Valid only in | |||
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| D4 | PMD2 | Ch.2 parity mode selection | 1 |
| Odd |
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| 0 |
| Even | X | R/W | asynchronous mode. | |
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| D3 | STPB2 | Ch.2 stop bit selection | 1 |
| 2 bits |
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| 0 |
| 1 bit | X | R/W |
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| D2 | SSCK2 | Ch.2 input clock selection | 1 |
| #SCLK2 |
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| 0 |
| Internal clock | X | R/W |
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| D1 | SMD21 | Ch.2 transfer mode selection | SMD2[1:0] |
| Transfer mode | X | R/W |
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| D0 | SMD20 |
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| 1 |
| 1 | X |
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| 1 |
| 0 |
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| 0 |
| 1 |
| Clock sync. Slave |
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| 0 |
| 0 | Clock sync. Master |
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Serial I/F Ch.2 | 00401F4 | – | reserved |
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| – |
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| – | – | 0 when being read. | ||
IrDA register | (B) | D4 | DIVMD2 | Ch.2 async. clock division ratio | 1 |
| 1/8 |
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| 0 |
| 1/16 | X | R/W |
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| D3 | IRTL2 | Ch.2 IrDA I/F output logic inversion | 1 |
| Inverted |
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| 0 |
| Direct | X | R/W | Valid only in | ||
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| D2 | IRRL2 | Ch.2 IrDA I/F input logic inversion | 1 |
| Inverted |
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| 0 |
| Direct | X | R/W | asynchronous mode. | ||
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| D1 | IRMD21 | Ch.2 interface mode selection | IRMD2[1:0] |
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| I/F mode | X | R/W |
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| D0 | IRMD20 |
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| 1 |
| 1 |
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| reserved | X |
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| 1 |
| 0 |
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| IrDA 1.0 |
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| 0 |
| 1 |
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| reserved |
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| 0 |
| 0 |
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| General I/F |
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SIF
S1C33L03 FUNCTION PART | EPSON |