II CORE BLOCK: BCU (Bus Control Unit)

Operation in successive RAS mode

Example: RAS: 2 cycles; CAS: 1 cycle; Precharge: 2 cycles

(1)

 

 

(2)

 

(3)

 

 

 

(4)

 

 

 

 

 

RAS

 

CAS cycles

Deassert

Assert

CAS cycles

Precharge

 

RAS

 

CAS

cycle

 

in page mode

 

 

cycle

 

cycle

in page mode

cycle

 

cycle

cycles

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BCLK

A[11:0]

#RASx

#HCAS/

#LCAS

#DRD

#DWE

Accsess to other

Not asserted for areas

device than DRAM

other than DRAM

Figure 4.35 Operation in Successive RAS Mode

(1)When accessing the DRAM area, an ordinary RAS cycle is executed first.

(2)If access to the same DRAM is suspended during a page mode, #RASx remains asserted while some other device is accessed. In this case, a cycle to temporarily deassert #DRD/#DWE is inserted before accessing the other device.

(3)If access to the same page in the same DRAM area as in (1) is requested after (2), #DRD/#DWE is asserted back again to restart the page mode.

(4)A precharge cycle is executed when one of the following conditions that cause the page mode to suspend is encountered:

•access to different DRAM is requested;

•access to a different page in the same DRAM area is requested;

•access to some other device than DRAM is requested;

•CAS-before-RAS refresh is requested; and

•relinquishing of bus control is requested by an external bus master.

Note: When using the successive RAS mode, always be sure to use #DRD for the read signal and #DWE for the low-byte write signal.

B-II-4-30

EPSON

S1C33L03 FUNCTION PART