4 PERIPHERAL CIRCUITS
Register name | Address | Bit | Name | Function |
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| Setting | Init. | R/W | Remarks | ||||
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0048240 | DF | TC2_L7 | Ch.2 transfer counter[7:0] |
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| X | R/W |
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DMA Ch.2 | (HW) | DE | TC2_L6 | (block transfer mode) |
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| X |
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transfer |
| DD | TC2_L5 |
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| X |
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counter |
| DC | TC2_L4 | Ch.2 transfer counter[15:8] |
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| X |
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register |
| DB | TC2_L3 | (single/successive transfer mode) |
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| X |
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| DA | TC2_L2 |
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| X |
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| D9 | TC2_L1 |
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| X |
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| D8 | TC2_L0 |
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| X |
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| D7 | BLKLEN27 | Ch.2 block length |
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| X | R/W |
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| D6 | BLKLEN26 | (block transfer mode) |
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| X |
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| D5 | BLKLEN25 |
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| X |
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| D4 | BLKLEN24 | Ch.2 transfer counter[7:0] |
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| X |
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| D3 | BLKLEN23 | (single/successive transfer mode) |
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| X |
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| D2 | BLKLEN22 |
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| X |
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| D1 | BLKLEN21 |
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| X |
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| D0 | BLKLEN20 |
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| X |
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0048242 | DF | DUALM2 | Ch.2 address mode selection | 1 |
| Dual addr | 0 |
| Single addr | 0 | R/W |
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DMA Ch.2 | (HW) | DE | D2DIR | D) Invalid |
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| – |
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| – | – |
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control register |
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| S) Ch.2 transfer direction control | 1 |
| Memory WR | 0 |
| Memory RD | 0 | R/W |
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| – | reserved |
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| – |
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| – | – | Undefined in read. | |
Note: |
| D7 | TC2_H7 | Ch.2 transfer counter[15:8] |
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| X | R/W |
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D) Dual address |
| D6 | TC2_H6 | (block transfer mode) |
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| X |
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mode |
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| D5 | TC2_H5 |
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| X |
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S) Single |
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| D4 | TC2_H4 | Ch.2 transfer counter[23:16] |
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| X |
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address |
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| D3 | TC2_H3 | (single/successive transfer mode) |
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| X |
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mode |
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| D2 | TC2_H2 |
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| X |
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| D1 | TC2_H1 |
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| X |
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| D0 | TC2_H0 |
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| X |
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0048244 | DF | S2ADRL15 | D) Ch.2 source address[15:0] |
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| X | R/W |
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DMA Ch.2 | (HW) | DE | S2ADRL14 | S) Ch.2 memory address[15:0] |
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| X |
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| DD | S2ADRL13 |
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| X |
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source address |
| DC | S2ADRL12 |
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| X |
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| DB | S2ADRL11 |
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| X |
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| DA | S2ADRL10 |
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| X |
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Note: |
| D9 | S2ADRL9 |
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| X |
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D) Dual address |
| D8 | S2ADRL8 |
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| X |
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mode |
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| D7 | S2ADRL7 |
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| X |
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S) Single |
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| D6 | S2ADRL6 |
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| X |
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address |
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| D5 | S2ADRL5 |
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| X |
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mode |
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| D4 | S2ADRL4 |
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| X |
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| D3 | S2ADRL3 |
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| X |
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| D2 | S2ADRL2 |
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| X |
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| D1 | S2ADRL1 |
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| X |
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| D0 | S2ADRL0 |
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| X |
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0048246 | DF | – | reserved |
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| – |
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| – | – |
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DMA Ch.2 | (HW) | DE | DATSIZE2 | Ch.2 transfer data size | 1 |
| Half word | 0 |
| Byte | 0 | R/W |
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| DD | S2IN1 | D) Ch.2 source address control | S2IN[1:0] |
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| Inc/dec | 0 | R/W |
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source address |
| DC | S2IN0 | S) Ch.2 memory address control |
| 1 | 1 |
| Inc.(no init) | 0 |
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| 1 | 0 |
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| Inc.(init) |
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| 0 | 1 |
| Dec.(no init) |
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Note: |
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| 0 | 0 |
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| Fixed |
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D) Dual address |
| DB | S2ADRH11 | D) Ch.2 source address[27:16] |
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| X | R/W |
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mode |
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| DA | S2ADRH10 | S) Ch.2 memory address[27:16] |
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| X |
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S) Single |
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| D9 | S2ADRH9 |
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| X |
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address |
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| D8 | S2ADRH8 |
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| X |
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mode |
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| D7 | S2ADRH7 |
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| X |
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| D6 | S2ADRH6 |
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| X |
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| D5 | S2ADRH5 |
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| X |
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| D4 | S2ADRH4 |
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| X |
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| D3 | S2ADRH3 |
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| X |
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| D2 | S2ADRH2 |
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| X |
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| D1 | S2ADRH1 |
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| X |
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| D0 | S2ADRH0 |
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| X |
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S1C33L03 PRODUCT PART | EPSON |