Epson S1C33L03 manual 512

VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE

Figure 2.12 shows an example of a timing chart in cases where the row address is varied during burst read.

BCLK

Command	NOP PRE	NOP ACTV	NOP	READ NOP	PRE	NOP	ACTV NOP	READ NOP
SDCKE	H
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]	BA	BA		BA	BA		BA	BA
SDA[10]		ROW1					ROW2
SDA[12:11, 9:0]		ROW1		COLn			ROW2	COL0
LDQM/HDQM
DQ[15:0]				D(n)	D(n+1)	D(n+2)		D(0) D(1) D(2)
		tRP	tRCD	CAS latency		tRP	tRCD	CAS latency
				= 2				= 2

tRAS

Figure 2.12 Changing Row Address During Burst Read

Single Read/Single Write

If the burst length is set to "1" (SDRBL[1:0] = "00"), the SDRAM controller reads data from the SDRAM in a single operation.

When writing to the SDRAM, data are always written in a single operation, no matter what burst length is selected.

BCLK

Command	NOP PRE	NOP ACTV	NOP	READ NOP	PRE	NOP	ACTV NOP	WRIT
SDCKE	H
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]	BA1	BA1		BA1	BA2		BA2	BA2
SDA[10]		ROW1					ROW2
SDA[12:11, 9:0]		ROW1		COL1			ROW2	COL2
LDQM/HDQM
DQ[15:0]					D(1)			D(2)
		tRP	tRCD	CAS latency		tRP	tRCD
				= 2

Figure 2.13 Single Read to Single Write (different page)

BCLK

Command	NOP PRE	NOP ACTV	NOP	READ	NOP	WRIT NOP	PRE NOP
SDCKE	H
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]	BA	BA		BA		BA	BA
SDA[10]		ROW1
SDA[12:11, 9:0]		ROW1		COLn		COLm
LDQM/HDQM
DQ[15:0]					D(n) D(n+1) D(n+2)	D(m)
		tRP	tRCD	CAS latency
					= 2

Figure 2.14 Burst Read to Single Write (same page)

B-VI-2-16 EPSON S1C33L03 FUNCTION PART