8 ELECTRICAL CHARACTERISTICS
SDRAM access cycle
| Bank active | Read/write | nop | nop | Precharge | ||
BCLK |
|
|
|
|
|
|
|
SDCKE | H |
|
|
|
|
|
|
| tAD |
|
|
|
|
|
|
A[23:0] | valid | valid |
|
|
| valid | |
| (Bank, Row) | (Column) |
|
|
| ||
| tA10D |
|
|
|
|
|
|
SDA10 | valid | valid |
|
|
| valid | |
| tCED1 |
|
| tCED2 |
|
|
|
#SDCEx |
|
|
|
|
|
|
|
| tRASD1 | tRASD2 |
|
|
|
|
|
#SDRAS |
|
|
|
|
|
|
|
|
| tCASD1 |
| tCASD2 |
|
|
|
#SDCAS |
|
|
|
|
|
|
|
| tWED1 |
|
| tWED2 |
|
|
|
#SDWE (read) |
|
|
|
|
|
| |
|
|
|
|
| tRDS | tRDH |
|
D[15:0] |
|
|
|
| valid | valid | |
HDQM/ | tDQMD1 |
|
|
|
|
| tDQMD2 |
|
|
|
|
|
|
| |
LDQM |
|
|
|
|
|
|
|
|
| tWED1 |
| tWED2 |
|
|
|
#SDWE (write) |
|
|
|
|
|
| |
| tWDD |
|
|
| tWDH |
|
|
D[15:0] |
| valid |
|
|
|
| |
∗ Read: CAS latency = 2, burst length = 2 | Write: single write |
|
| ||||
SDRAM |
|
|
|
|
| ||
| Mode register set | nop |
| nop | nop | nop | |
BCLK |
|
|
|
|
|
|
|
SDCKE H
tAD
A[23:0]valid
tAD
SDA10valid
|
| tCED1 |
|
| tCED2 | ||
|
|
| |||||
#SDCEx |
|
|
| ||||
|
|
|
|
|
|
| tRASD2 |
|
| tRASD1 |
|
| |||
|
|
|
| ||||
#SDRAS |
|
|
| ||||
|
| tCASD1 |
|
| tCASD2 | ||
|
|
|
| ||||
#SDCAS |
|
|
| ||||
|
| tWED1 |
|
| tWED2 | ||
|
|
| |||||
#SDWE
D[15:0]
HDQM/
LDQM
S1C33L03 PRODUCT PART | EPSON |