VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
SDRPC1: #CE8/14 pin configuration (D2) / SDRAM area configuration register (0x39FFC0)
SDRPC0: #CE7/13 pin configuration (D3) / SDRAM area configuration register (0x39FFC0)
Set the
Write "1": #SDCEx (for SDRAM)
Write "0": #CExx (for other devices)
Read: Valid
Select the pin to be used as a chip enable for the SDRAM connected to the S1C33. Write "1" to SDRPC0 to set the #CE7/13 pin for SDRAM use (#SDCE0). Similarly, write "1" to SDRPC1 to set the #CE8/14 pin for SDRAM use (#SDCE1). Writing "0" to either bit sets the corresponding pin to be used as
SDRAMs and the BCU are used
At cold start, these bits are set to "0" (#CExx). At hot start, these bits retain their status before being initialized.
SDRENA: Enable SDRAM signals (D7) / SDRAM control register (0x39FFC1)
Enable the pins used for the SDRAM.
Write "1": Enabled
Write "0": Disabled
Read: Valid
Writing "1" to SDRENA sets the pins shared with other functions to be used for the SDRAM, with the SDRAM clock output from the BCLK pin. If SDRENA = "0", the shared pins serve other functions.
The SDRAM clock output from the BCLK pin is stopped in the HALT2 and the SLEEP modes.
At cold start, SDRENA is set to "0" (disabled). At hot start, SDRENA retains its status before being initialized.
SDRINI: Initialize SDRAM (D6) / SDRAM control register (0x39FFC1)
Initiate the SDRAM initialization sequence.
Write "1": | Start |
Write "0": | No operation |
Read: | Valid |
Writing "1" to SDRINI initiates the SDRAM initialization sequence at SDRAM
At cold or hot start, SDRINI is set to "0".
SDRSRF: Enable SDRAM
Enable the SDRAM's
Write "1": Enabled
Write "0": Disabled
Read: Valid
Writing "1" to SDRSRF enables the SDRAM controller to start
SDRSRF = "0" disables the
At cold start, SDRSRF is set to "0" (disabled). At hot start, SDRSRF retains its status before being initialized.
SDRAM
S1C33L03 FUNCTION PART | EPSON |