Epson S1C33L03 manual 507

VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE

A-1

Timing setup

The following parameters can be set in conformity with SDRAM specifications before use.

Table 2.10 SDRAM Parameters

Symbol	SDRAM parameter	Set values	Control bits
		(# of clocks)
tRC	ACTIVE to ACTIVE command period	1 to 8	SDRTRC[2:0] (D[2:0])/SDRAM
	AUTO REFRESH command period		timing set-up register 1 (0x39FFC4)
	Exit SELF REFRESH to ACTIVE command period
tRAS	ACTIVE to PRECHARGE command period	1 to 8	SDRTRAS[2:0] (D[7:5])/SDRAM
	Minimum SELF REFRESH period		timing set-up register 1 (0x39FFC4)
tRCD	ACTIVE to READ or WRITE delay time	1 to 4	SDRTRCD[1:0] (D[7:6])/SDRAM
			timing set-up register 2 (0x39FFC5)
tRP	PRECHARGE command period	1 to 4	SDRTRP[1:0] (D[4:3])/SDRAM
			timing set-up register 1 (0x39FFC4)
tRRD	ACTIVE bank (a) to ACTIVE bank (b) period	1 to 4	SDRTRRD[1:0] (D[4:3])/SDRAM
			timing set-up register 2 (0x39FFC5)
tRSC	MODE REGISTER SET cycle time	1 or 2	SDRTRSC (D5)/SDRAM timing set-
			up register 2 (0x39FFC5)

BCLK

Command	NOP	ACTV	NOP	READ	NOP	NOP	NOP	PRE	NOP	ACTV
SDBA[1:0]		BA		BA				BA		BA
SDA[12:11, 9:0]		ROW		COL						ROW
SDA10		ROW						BKsel		ROW
DQ[15:0]						DATA	DATA	DATA	DATA
			tRCD	CAS latency
					tRAS				tRP
						tRC		(Burst length = 4)
				(a) Burst read
BCLK
Command	NOP	ACTV	NOP	READ	NOP	ACTV	NOP	READ	NOP	NOP
SDBA[1:0]		BAa		BAa		BAb		BAb
SDA[12:11, 9:0]		ROWa		COLa		ROWb		COLb
SDA10		ROWa				ROWb
DQ[15:0]						Da	Da+1	Da+2	Da+3	Db

tRRD

(Burst length = 4)

(b) Bank interleaved access Figure 2.7 SDRAM Parameters

Note: When the auto-refresh command is executed, the following command may be issued 3 or 4

CPU_CLK cycles from that point regardless of the tRC value set in the SDRTRC[2:0] (D[2:0])/SDRAM timing set-up register 1 (0x39FFC4). Therefore, use SDRAMs with 75 ns or less of tRC.

B-VI

SDRAM

S1C33L03 FUNCTION PART EPSON B-VI-2-11