BL:
CL: tRP: tRCD:

VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE

SDRTRCD1–SDRTRCD0: SDRAM tRCD spec (D[7:6]) / SDRAM timing set-up register 2 (0x39FFC5)

Set the tRCD SDRAM parameter (ACTIVE to READ or WRITE delay time).

In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM clock cycles. Specifying 1–3 sets the period to 1–3 clock cycles. Specifying 0 sets the period to 4 clock cycles. At cold start, SDRTRCD is set to "00" (4). At hot start, SDRTRCD retain its status before being initialized.

SDRTRSC: SDRAM tRSC spec (D5) / SDRAM timing set-up register 2 (0x39FFC5)

Set the tRSC SDRAM parameter (Mode Register Set cycle time).

Write "1": 1 clock

Write "0": 2 clocks

Read: Valid

In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM clock cycles.

At cold start, SDRTRSC is set to "0" (2). At hot start, SDRTRSC retain its status before being initialized.

SDRTRRD1–SDRTRRD0: SDRAM tRRD spec (D[4:3]) / SDRAM timing set-up register 2 (0x39FFC5)

Set the tRRD SDRAM parameter (ACTIVE bank (a) to ACTIVE bank (b) period).

In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM clock cycles. Specifying 1–3 sets the period to 1–3 clock cycles. Specifying 0 sets the period to 4 clock cycles. At cold start, SDRTRRD is set to "00" (4). At hot start, SDRTRRD retain its status before being initialized.

SDRARFC11–SDRARFC0:SDRAM auto refresh count (D[B:0]) / SDRAM auto refresh count register (0x39FFC6)

Set the auto refresh counter value.

The auto-refresh counter counts up on the OSC3 clock edges beginning with 0, and when the count specified here is reached, the SDRAM controller sends an auto-refresh command. The counter is reset at that point, and starts counting the next refresh period. The counter is also reset by self-refresh.

The value calculated from the equation below is the maximum count that can be set.

RFP

SDRARFC ≤ –––––––– ⋅ fOSC3 - BL - CL - 2 ⋅ tRP - tRCD - 3

ROWS

RFP: Maximum refresh period [s]

ROWS: Row address size

fOSC3: OSC3 clock frequency [Hz]

Burst length [word]

CAS latency [Number of SD_CLK clocks]

PRECHARGE command period [Number of SD_CLK clocks] ACTIVE to READ or WRITE delay time [Number of SD_CLK clocks]

At cold start, SDRARFC is set to "0xFFF" (4095). At hot start, SDRARFC retain its status before being initialized.

SDRSRFC3–SDRSRFC0:SDRAM self refresh count (D[3:0]) / SDRAM self refresh count register (0x39FFC8)

Set the self refresh counter value.

If SDRSRF (D5/0x39FFC1) is set to "1" (self-refresh-enabled), the self-refresh counter starts counting up on the SDRAM clock edges beginning with 0 after accessing or auto-refreshing the SDRAM. When the count specified here is reached, the SDCKE output is pulled low, causing the SDRAM to start self-refreshing. If an access to the SDRAM occurs during self-refresh mode, SDCKE is returned high, thereby taking the SDRAM out of self-refresh mode.

At cold start, SDRSRFC is set to "0xF" (15). At hot start, SDRSRFC retain its status before being initialized.

Note: Always set this register to 2 or more. If it is set to less than 2, the SDRAM cannot exit self-refresh mode.

B-VI-2-30

EPSON

S1C33L03 FUNCTION PART