III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
Key Input Interrupt
The key input interrupt circuit has two interrupt systems (FPK1 and FPK0) and a port group can be selected for generating each interrupt factor.
The interrupt condition can also be set by software.
Figure 9.4 shows the configuration of the port input interrupt circuit.
Internal data bus
FPK0 system
K50 
K60 
P00 
P20 
| Interrupt signal | FPK0 | |
Input port selection | Interrupt | ||
generation | |||
SPPK0 | request | ||
|
Input comparison
register SCPK0
Address 
Input mask
register SMPK0
Address 
K50, K60, P00, P20
K51, K61, P01, P21
K52, K62, P02, P22
K53, K63, P03, P23
K54, K64, P04, P24
FPK1 system
K60 
K64 
P04 
P24 |
| FPK1 | |
| Interrupt signal | ||
Input port selection | Interrupt | ||
generation | |||
request | |||
SPPK1 |
| ||
|
|
Input comparison
register SCPK1
Address 
Input mask
register SMPK1
Address 
K60, K64, P04, P24
K61, K65, P05, P25
K62, K66, P06, P26
K63, K67, P07, P27
Figure 9.4 Configuration of Key Input Interrupt Circuit
EPSON | S1C33L03 FUNCTION PART |