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| I OUTLINE: LIST OF PINS |
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Pin name | Pin No. | I/O |
| Function | |
P11 | 121 | I/O | – | P11: | I/O port when CFP11(D1/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0" |
EXCL1 |
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| EXCL1: | |
T8UF1 |
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| IOC11(D1/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" |
DST1 |
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| T8UF1: | |
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| = "1" and CFEX1(D1/0x402DF) = "0" |
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| DST1: | DST1 signal output when CFEX1(D1/0x402DF) = "1" (default) |
P12 | 120 | I/O | – | P12: | I/O port when CFP12(D2/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0" |
EXCL2 |
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| EXCL2: | |
T8UF2 |
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| IOC12(D2/0x402D6) = "0" and CFEX0(D0/0x402DF) = "0" |
DST2 |
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| T8UF2: | |
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| = "1" and CFEX0(D0/0x402DF) = "0" |
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| DST2: | DST2 signal output when CFEX0(D0/0x402DF) = "1" (default) |
P13 | 119 | I/O | – | P13: | I/O port when CFP13(D3/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0" |
EXCL3 |
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| EXCL3: | |
T8UF3 |
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| IOC13(D3/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0" |
DPCO |
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| T8UF3: | |
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| = "1" and CFEX1(D1/0x402DF) = "0" |
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| DPCO: | DPCO signal output when CFEX1(D1/0x402DF) = "1" (default) |
P14 | 118 | I/O | – | P14: | I/O port when CFP14(D4/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0" |
FOSC1 |
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| FOSC1: | OSC1 clock output when CFP14(D4/0x402D4) = "1" and |
DCLK |
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| CFEX0(D0/0x402DF) = "0" |
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| DCLK: | DCLK signal output when CFEX0(D0/0x402DF) = "1" (default) |
P15 | 84 | I/O | – | P15: | I/O port when CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) |
EXCL4 |
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| = "0" (default) |
#DMAEND0 |
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| EXCL4: | |
#SCLK3 |
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| IOC15(D5/0x402D6) = "0" and SDRENA(D7/0x39FFC1) = "0" |
LDQM |
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| #DMAEND0: HSDMA Ch. 0 | |
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| = "1", IOC15(D5/0x402D6) = "1" and SDRENA(D7/0x39FFC1) = "0" |
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| #SCLK3: | Serial I/F Ch. 3 clock input/output when SSCLK3(D2/0x402D7) = "1", |
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| CFP15(D5/0x402D4) = "0" and SDRENA(D7/0x39FFC1) = "0" |
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| LDQM: | SDRAM data (low byte) input/output mask signal when |
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| SDRENA(D7/0x39FFC1) = "1" |
P16 | 83 | I/O | – | P16: | I/O port when CFP16(D6/0x402D4) = "0" (default) |
EXCL5 |
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| EXCL5: | |
#DMAEND1 |
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| IOC16(D6/0x402D6) = "0" |
SOUT3 |
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| #DMAEND1: HSDMA Ch. 1 | |
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| "1" and IOC16(D6/0x402D6) = "1" |
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| SOUT3: | Serial I/F Ch. 3 data output when SSOUT3(D1/0x402D7) = "1" and |
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| CFP16(D6/0x402D4) = "0" |
P20 | 80 | I/O | – | P20: | I/O port when CFP20(D0/0x402D8) = "0" and SDRENA(D7/0x39FFC1) |
#DRD |
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| = "0" (default) |
SDCKE |
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| #DRD: | DRAM read signal output for successive RAS mode when |
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| CFP20(D0/0x402D8) = "1" and SDRENA(D7/0x39FFC1) = "0" |
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| SDCKE: | SDRAM clock enable signal when SDRENA(D7/0x39FFC1) = "1" |
P21 | 79 | I/O | – | P21: | I/O port when CFP21(D1/0x402D8) = "0", CFEX2(D2/0x402DF) = "0" and |
#DWE |
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| SDRENA(D7/0x39FFC1) = "0" (default) |
#GAAS |
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| #DWE: | DRAM write signal output for successive RAS mode when |
#SDWE |
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| CFP21(D1/0x402D8) = "1", CFEX2(D2/0x402DF) = "0" and |
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| SDRENA(D7/0x39FFC1) = "0" |
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| #GAAS: | Area address strobe output for GA when CFEX2(D2/0x402DF) = "1" and |
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| SDRENA(D7/0x39FFC1) = "0" |
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| #SDWE: | SDRAM write signal when SDRENA(D7/0x39FFC1) = "1" |
P22 | 1 | I/O | – | P22: | I/O port when CFP22(D2/0x402D8) = "0" (default) |
TM0 |
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| TM0: | |
P23 | 2 | I/O | – | P23: | I/O port when CFP23(D3/0x402D8) = "0" (default) |
TM1 |
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| TM1: | |
P24 | 4 | I/O | – | P24: | I/O port when CFP24(D4/0x402D8) = "0" (default) |
TM2 |
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| TM2: | |
#SRDY2 |
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| #SRDY2: | Serial I/F Ch. 2 ready signal input/output when SSRDY2(D3/0x402DB) = "1" |
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| and CFP24(D4/0x402D8) = "0" |
P25 | 5 | I/O | – | P25: | I/O port when CFP25(D5/0x402D8) = "0" (default) |
TM3 |
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| TM3: | |
#SCLK2 |
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| #SCLK2: | Serial I/F Ch. 2 clock input/output when SSCLK2(D2/0x402DB) = "1" and |
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| CFP25(D5/0x402D8) = "0" |
Pin
S1C33L03 FUNCTION PART | EPSON |