Epson S1C33L03 manual 510

VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE

SDRAM power	VCC(Min.)
BCLK
Command	NOP PALL		MRS	REF	REF	CMD
SDCKE	H
#SDCEx
#SDRAS
#SDCAS
#SDWE
HDQM/LDQM	H
SDRENA bit
SDRIS bit
SDRINI bit
SDRMRS bit
Internal #WAIT
SDA10			Valid			Valid
SDBA[1:0]			Valid			Valid
SDA[12:11, 9:0]			Valid			Valid
	100 ∝s min.	tRP		tRSC	tRC	tRC
	Figure 2.10	SDRAM Power-up and Initialization

SDRAM Commands

The SDRAM is controlled by commands that are comprised of a combination of high or low logic level signals. Table 2.11 lists the commands output by the SDRAM controller.

Table 2.11 List of the Supported SDRAM Commands

Command							Pins
				DQM	Bank		SDA
Function	Symbol	SDCKE				SDA10	A[13:12]	#SDCEx	#SDRAS	#SDCAS	#SDWE
				H/LDQM	A[15:14]
							A[10:1]
Bank Active	ACTV	H		X	V	V	V	L	L	H	H
Bank Precharge	PRE	H		X	V	L	X	L	L	H	L
Precharge All	PALL	H		X	X	H	X	L	L	H	L
Write	WRIT	H		X	V	L	V	L	H	L	L
Read	READ	H		X	V	L	V	L	H	L	H
Mode Register Set	MRS	H		X	V	V	V	L	L	L	L
Deselect / NOP	NOP	H		X	X	X	X	H	X	X	X
Auto Refresh	REF	H		X	X	X	X	L	L	L	H
Self Refresh Entry	SELF	H →	L	X	X	X	X	L	L	L	H
Self Refresh Exit	–	L →	H	X	X	X	X	H	X	X	X
Data Write/Output	–	H		L	X	X	X	X	X	X	X
Enable
Data Write/Output	–	H		H	X	X	X	X	X	X	X
Disable

V = valid, X = don’t care, L = low level, H = high level

Because all of these commands are output by the SDRAM controller as necessary, they do not need to be controlled by a user program, except for the commencement of initialization by SDRINI.

B-VI-2-14 EPSON S1C33L03 FUNCTION PART