Epson S1C33L03 180

II CORE BLOCK: BCU (Bus Control Unit)

Memory Area

Memory Map

Figure 4.1 shows the memory map supported by the BCU.

Area	Address
Area 9	0x0BFFFFF
SRAM type
Burst ROM type
8 or 16 bits	0x0800000
Area 8	0x07FFFFF
SRAM type
DRAM type
8 or 16 bits	0x0600000
Area 7	0x05FFFFF
SRAM type
DRAM type
8 or 16 bits	0x0400000
Area 6	0x03FFFFF
SRAM type	0x0380000
	0x037FFFF
	0x0300000
Area 5	0x02FFFFF
SRAM type
8 or 16 bits
	0x0200000
Area 4	0x01FFFFF
SRAM type
8 or 16 bits
	0x0100000
Area 3	0x00FFFFF
16 bits
Fixed at 1 cycle
	0x0080000
Area 2	0x007FFFF
16 bits
Fixed at 3 cycles
	0x0060000
Area 1	0x005FFFF
8, 16 bits	0x0050000
2 or 4 cycles	0x004FFFF
	0x0040000
	0x003FFFF
	0x0030000
Area 0	0x002FFFF
32 bits
Fixed at 1 cycle
	0x0000000

External memory (4MB)

External memory (2MB)

External I/O (16-bit device)

External I/O (8-bit device)

External memory (1MB)

(Reserved)

For middleware use

(Reserved)

For CPU core or debug mode

(Mirror of internal I/O)

Internal I/O

(Mirror of internal I/O)

Internal RAM

Area	Address
Area 18	0xFFFFFFF
SRAM type	0xD000000
8 or 16 bits	0xCFFFFFF
	0xC000000
Area 17	0xBFFFFFF
SRAM type	0x9000000
8 or 16 bits	0x8FFFFFF
	0x8000000
Area 16	0x7FFFFFF
SRAM type	0x7000000
8 or 16 bits	0x6FFFFFF
	0x6000000
Area 15	0x5FFFFFF
SRAM type	0x5000000
8 or 16 bits	0x4FFFFFF
	0x4000000
Area 14	0x3FFFFFF
SRAM type
DRAM type
8 or 16 bits	0x3000000
Area 13	0x2FFFFFF
SRAM type
DRAM type
8 or 16 bits	0x2000000
Area 12	0x1FFFFFF
SRAM type
8 or 16 bits
	0x1800000
Area 11	0x17FFFFF
SRAM type
8 or 16 bits
	0x1000000
Area 10	0x0FFFFFF
SRAM type
Burst ROM type
8 or 16 bits	0x0C00000

External memory (16MB)

External memory (8MB)

External memory (4MB)

Figure 4.1 Memory Map

Basically, Areas 0 to 3 are internal memory areas and Areas 4 to 18 are external memory areas.

Area 0 is normally used for a built-in RAM. The built-in memory is mapped from the beginning of the area.

Area 1 is reserved for the I/O memory of the on-chip functional blocks. Address 0x0040000 to address 0x004FFFF are used as the control registers and address 0x0050000 to 0x005FFFF are used as the mirror area.

Area 2 is used in debug mode only and it cannot be accessed in user mode (normal program execution status). Area 3 is reserved for S1C33 middlewares.

Area 4 to 18 can also be configured as internal memory areas using the control register and they can be used for user logic circuits.

Note: Addresses 0x39FFC0–0x39FFCD in Area 6 are reserved as the internal memory area for the control I/O memory of the SDRAM controller. Pay attention to this area since it must be accessed when controlling the SDRAM self-refresh mode or other SDRAM functions.

B-II-4-4

EPSON

S1C33L03 FUNCTION PART