III PERIPHERAL BLOCK: CLOCK TIMER
Register name | Address | Bit | Name | Function |
| Setting |
| Init. | R/W | Remarks | ||
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Clock timer | 0040159 | – | reserved |
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| – |
| – | – | 0 when being read. | ||
minute | (B) | D5 | TCCH5 | Clock timer minute comparison |
| 0 to 59 minutes | X | R/W |
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comparison |
| D4 | TCCH4 | data | (Note) Can be set within | X |
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register |
| D3 | TCCH3 | TCCH5 = MSB |
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| X |
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| D2 | TCCH2 | TCCH0 = LSB |
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| X |
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| D1 | TCCH1 |
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| X |
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| D0 | TCCH0 |
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| X |
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Clock timer | 004015A | – | reserved |
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| – |
| – | – | 0 when being read. | ||
hour | (B) | D4 | TCCD4 | Clock timer hour comparison data |
| 0 to 23 hours | X | R/W |
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comparison |
| D3 | TCCD3 | TCCD4 = MSB | (Note) Can be set within | X |
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register |
| D2 | TCCD2 | TCCD0 = LSB |
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| X |
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| D1 | TCCD1 |
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| X |
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| D0 | TCCD0 |
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| X |
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Clock timer | 004015B | – | reserved |
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| – | – | 0 when being read. | ||
day | (B) | D4 | TCCN4 | Clock timer day comparison data |
| 0 to 31 days | X | R/W | Compared with | |||
comparison |
| D3 | TCCN3 | TCCN4 = MSB |
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| X |
| TCND[4:0]. |
register |
| D2 | TCCN2 | TCCN0 = LSB |
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| X |
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| D1 | TCCN1 |
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| X |
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| D0 | TCCN0 |
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| X |
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Clock timer | 004026B | – | reserved |
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| – |
| – | – | Writing 1 not allowed. | ||
interrupt | (B) | D2 | PCTM2 | Clock timer interrupt level |
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| 0 to 7 |
| X | R/W |
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priority register |
| D1 | PCTM1 |
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| X |
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| D0 | PCTM0 |
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| X |
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Port input | 0040277 | – | reserved |
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| – |
| – | – | 0 when being read. | ||
clock timer, | (B) | D5 | EP7 | Port input 7 | 1 | Enabled |
| 0 | Disabled | 0 | R/W |
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A/D interrupt |
| D4 | EP6 | Port input 6 |
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| 0 | R/W |
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enable register |
| D3 | EP5 | Port input 5 |
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| 0 | R/W |
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| D2 | EP4 | Port input 4 |
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| 0 | R/W |
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| D1 | ECTM | Clock timer |
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| 0 | R/W |
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| D0 | EADE | A/D converter |
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| 0 | R/W |
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Port input | 0040287 | – | reserved |
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| – | – | 0 when being read. | ||
clock timer, A/D | (B) | D5 | FP7 | Port input 7 | 1 | Factor is |
| 0 | No factor is | X | R/W |
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interrupt factor |
| D4 | FP6 | Port input 6 |
| generated |
| generated | X | R/W |
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flag register |
| D3 | FP5 | Port input 5 |
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| X | R/W |
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| D2 | FP4 | Port input 4 |
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| X | R/W |
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| D1 | FCTM | Clock timer |
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| X | R/W |
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| D0 | FADE | A/D converter |
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| X | R/W |
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TCRST: Clock timer reset (D1) / Clock timer Run/Stop register (0x40151)
Resets the clock timer.
Write "1": The clock timer is reset
Write "0": Invalid
Read: Always "0"
The clock timer is reset by writing "1" to TCRST when the timer is inactive. All timer counters are cleared to "0". The clock timer cannot be reset when in the RUN state, nor can it be reset at the same time it is made to RUN through the execution of one write to address 0x40151. (The clock timer is started, but not reset.) In this case, first reset the clock timer and then use another instruction to RUN the clock timer. When the counters are cleared as the clock timer is reset, an interrupt may be generated, depending on the register settings. Therefore, before resetting the clock timer, first disable the clock timer interrupt, and after resetting the clock timer, reset the interrupt factor flag and the interrupt factor and alarm factor generation flags.
Writing "0" to TCRST results in No Operation. Since this TCRST is a
The clock timer is not reset by an initial reset.
EPSON | S1C33L03 FUNCTION PART |