III PERIPHERAL BLOCK:
F8TUx is the interrupt factor flag corresponding to each timer. It is set to "1" when the counter underflows. At this time, if the following conditions are met, an interrupt to the CPU is generated:
1.The corresponding interrupt enable register bit is set to "1".
2.No other interrupt request of a higher priority has been generated.
3.The IE bit of the PSR is set to "1" (interrupts enabled).
4.The value set in the corresponding interrupt priority register is higher than the interrupt level (IL) of the CPU. When using the interrupt factor of the
The interrupt factor flag is set to "1" whenever interrupt generation conditions are met, regardless of how the interrupt enable and interrupt priority registers are set.
If the next interrupt is to be accepted after an interrupt has occurred, it is necessary that the interrupt factor flag be reset, and that the PSR be set again (by setting the IE bit to "1" after setting the IL to a value lower than the level indicated by the interrupt priority register, or by executing the reti instruction).
The interrupt factor flag can be reset only by writing to it in the software. Note that if the PSR is set again to accept interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the
At initial reset, the content of F8TUx becomes indeterminate, so be sure to reset it in the software.
R8TU0: Timer 0 IDMA request (D2) /
R8TU1: Timer 1 IDMA request (D3) /
R8TU2: Timer 2 IDMA request (D4) /
R8TU3: Timer 3 IDMA request (D5) /
Specifies whether IDMA is to be invoked at the occurrence of an interrupt factor.
When using the
Write "1": IDMA request
Write "0": Not changed
Read: Valid
When using the read/write method
Write "1": IDMA request
Write "0": Interrupt request
Read: Valid
R8TUx is the IDMA request bit for each timer. If this bit is set to "1", IDMA can be invoked when an interrupt factor occurs, and thus programmed data transfers are performed. If the bit is set to "0", normal interrupt processing is performed and IDMA is not invoked.
For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, R8TUx is set to "0" (interrupt request).
EPSON | S1C33L03 FUNCTION PART |