V DMA BLOCK: HSDMA
Timing Chart
(1) SRAM
Example: When 2 (RD)/1 (WR) wait cycles are inserted
| Read cycle | Write cycle |
BCLK |
|
|
A[23:0] | source address | destination address |
#CE(src)
#CE(dst)
#RD
#WRH/#WRL
#DMAEND
Figure 2.6 #DMAEND Signal Output Timing (SRAM)
(2) DRAM
Example: Page mode, RAS: 1 cycle; CAS: 2 cycles; Precharge: 1 cycle
|
| Read cycle |
|
| Write cycle |
|
BCLK |
|
|
|
|
|
|
A[11:0] | ROW | COL #1 | COL #2 | ROW | COL #1 | COL #2 |
#RASx
#HCAS/
#LCAS
#RD
#WR
#DMAEND
Figure 2.7 #DMAEND Signal Output Timing (DRAM)
HSDMA
S1C33L03 FUNCTION PART | EPSON |