VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
Programming Notes
(1)Make sure that two wait cycles are inserted when accessing area 6, where the SDRAM controller is allocated. With any other number of specified wait cycles, data may not be written normally to the SDRAM control registers.
(2)Set the area used for an SDRAM for internal access (A8IO (DA/0x48132) = "1" or A14IO (DD/0x48132) = "1").
(3)Before entering HALT2 or SLEEP mode, be sure to place the SDRAM in
If an access to the SDRAM occurs while being
(4)Do not access addresses 0x039FFCB to 0x039FFCD, as the user program will not be able to control the CPU.
(5)If the program accesses an area out of the address range set using the address setting register (0x39FFC2), an unintended area is accessed and the stored data may be overwritten. Therefore, do not access an area out of the set range.
EPSON | S1C33L03 FUNCTION PART |