VII LCD CONTROLLER BLOCK: LCD CONTROLLER

The following is the power-down procedure.

1.Place the LCD controller in power-save mode (LPSAVE = "0b00").

2.The LCD controller starts a power-down sequence and turns off the power to the LCD panel a one-frame period later, then pulls LCD signals low.

3.Because the bus clock is turned off during HALT2 or SLEEP mode, the one-frame period described above must elapse before the chip can be placed in standby mode.

The number of frames can be counted by reading VNDPF (D7)/vertical non-display period register (0x39FFEA) repeatedly. VNDPF is set to "1" during the vertical non-display period (set to "0" during the display period).

Depending on the power supply for the LCD panel, it may be necessary to secure more than one frame of power-on time, otherwise electricity may not be fully discharged within a one-frame period following power-off. In such a case, exclusive power-up/power-down sequences may be programmed. Control examples are shown below.

Example of a power-up sequence

(for controlling the length of time before the LCD power turns on after LCD signals are asserted)

1.Set LPWREN to "0". The LCDPWR signal is fixed low, with control by a power-up sequence disabled.

2.Release power-save mode (LPSAVE = "0b11").

3.The LCD signals go active a one-frame period after step 2.

4.Allow for a wait time until the power turns on. To set the wait time in terms of the number of frames, count the occurrences of VNDPF = "1" (vertical non-display period).

5.Set LPWREN to "1" a specified length of time later. The LCDPWR pin goes high, causing the power to the LCD panel to turn ON.

Example of a power-down sequence

(for controlling the length of time before LCD signals are deasserted after the LCD power turns off)

1.Set LPWREN to "0". The LCDPWR pin goes low, and the power to the LCD panel turns off.

2.Allow for a wait time until LCD signals are deasserted. To set the wait time in terms of the number of frames, count the occurrences of VNDPF = "1" (vertical non-display period).

3.Set power-save mode a specified length of time later (LPSAVE = "0b00").

4.LCD signals are deasserted a one-frame period after step 3.

Reading/Writing Display Data

The LCD controller contains an exclusive DMA interface, allowing data to be taken in from the display memory by means of DMA transfer. The display data read from the display memory is buffered in the internal 16 ⋅ 16-bit FIFO, preventing the bus efficiency from decreasing. If the data in the FIFO decreases to (0xf - FIFOEO[3:0]) words or less, the LCD controller outputs a DMA request to the CPU requesting that the data be read. Although any value from 0 to 0xf can be written to FIFOEO[3:0] (D[6:3])/FIFO control register (0x39FFF4), we recommend setting the value 8.

There are no timing limitations when data is written to the display memory by a user program using the above DMA transfer. Data can be written asynchronously with the display.

Setting the Display Start Address

The LCD controller is initially set in such a way that data is displayed beginning with the initial address of the display memory (the area selected by the VRAMAR bit). Because the display memory address from which to start display can be changed as desired using the screen 1 start address register (0x39FFEC–0x39FFED, D0/0x39FFF0), it is possible to set a virtual screen for panning or scrolling, as will be described later. The start address set in the screen 1 start address register corresponds to the upper left edge of the LCD panel.

The value that should actually be set in this register is an offset address from the beginning of the area in which the display memory exists. When area 7 is used, for example, the start address of the display memory is 0x0, rather than 0x400000. Be aware that the address set here is a halfword address (byte address for portrait mode; described later).

B-VII-2-22

EPSON

S1C33L03 FUNCTION PART