Epson S1C33L03 manual 511

VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE

A-1

Burst Read Cycle

Except when the burst length is set to 1 (SDRBL[1:0] ≠ "00"), the SDRAM controller always reads data from the SDRAM in bursts.

Figure 2.11 shows several examples of timing charts when reading out 4-word data from the same row address in varying burst lengths.

Example of parameter settings: CAS latency = 2, tRCD = 2 cycles, tRP = 2 cycles

(1) Burst length = 8

BCLK

Command	NOP PRE	NOP ACTV	NOP	READ NOP
SDCKE	H
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]	BA	BA		BA
SDA[10]		ROW
SDA[12:11, 9:0]		ROW		COL
LDQM/HDQM
DQ[15:0]				D(1)	D(2)	D(3)	D(4)	D(5)	D(6)
		tRP	tRCD	CAS latency
				= 2

(2) Burst length = 4

BCLK

Command	NOP	PRE	NOP	ACTV	NOP	READ	NOP
SDCKE	H
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]		BA		BA		BA
SDA[10]				ROW
SDA[12:11, 9:0]				ROW		COL
LDQM/HDQM
DQ[15:0]								D(1)	D(2)	D(3)	D(4)
			tRP		tRCD	CAS latency
							= 2
(3) Burst length = 2
BCLK
Command	NOP	PRE	NOP	ACTV	NOP	READ	NOP	READ	NOP
SDCKE	H
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]		BA		BA		BA		BA
SDA[10]				ROW
SDA[12:11, 9:0]				ROW		COL1		COL2
LDQM/HDQM
DQ[15:0]								D(1-1) D(1-2) D(2-1) D(2-2)
			tRP		tRCD	CAS latency CAS latency
							= 2		= 2

Figure 2.11 Burst Read in the Same Page

B-VI

SDRAM

S1C33L03 FUNCTION PART EPSON B-VI-2-15