II CORE BLOCK: BCU (Bus Control Unit)
Column address size
When accessing DRAM, addresses are divided into a row address and a column address as they are output. Choose the size of this column address using RCA, as shown below.
Table 4.18 Column Address Size
RCA1 | RCA0 | Column address size |
1 | 1 | 11 |
1 | 0 | 10 |
0 | 1 | 9 |
0 | 0 | 8 |
The initial default size is 8 bits. Choose the desired size according to the address input pins of the DRAM to be used.
The row addresses output synchronously with falling edges of the #RAS signal are derived from the CPU's internal
Figure 4.28 shows the contents of the row addresses thus output.
27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
| 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
(1) | Row address when column address is set to 8 bits |
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| T | T | T | T | T | T | T | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 |
| 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
(2) | Row address when column address is set to 9 bits |
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| T | T | T | T | T | T | T | T | 27 | 26 | 25 | 24 | 23 | 22 | 21 |
| 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
(3) | Row address when column address is set to 10 bits |
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| T | T | T | T | T | T | T | T | T | 27 | 26 | 25 | 24 | 23 | 22 |
| 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 |
(4) | Row address when column address is set to 11 bits |
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| T | T | T | T | T | T | T | T | T | T | 27 | 26 | 25 | 24 | 23 |
| 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 |
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| T = "1", |
Figure 4.28 Example of Row/Column Address Mapping
Refresh enable
Use RPC2 to enable or disable the internal refresh function.
RPC2 = "1": Enabled
RPC2 = "0": Disabled (default)
After choosing the desired refresh method using RPC1, write "1" to RPC2.
Refresh method
The DRAM interface supports both a
RPC1 = "1":
RPC1 = "0":
The generation interval of the
If RPC1 is switched over when RPC2 = "1" (refresh enabled), an undesirable
EPSON | S1C33L03 FUNCTION PART |