II CORE BLOCK: BCU (Bus Control Unit)
Bus Operation
Data Arrangement in Memory
The S1C33 Family of devices handle data in bytes (8 bits),
Table 4.12 shows the data arrangement in memory, classified by data type.
Table 4.12 Data Arrangement in Memory
Data type | Arranged location |
Byte data | Byte boundary address (all addresses) |
Word data | Word boundary address (A[1:0]="00") |
The
A16EC (D6): Areas 15 and 16
A14EC (D5): Areas 13 and 14
A12EC (D4): Areas 11 and 12
A10EC (D3): Areas 9 and 10 ... Fixed at "0"
A8EC (D2): Areas 7 and 8
A6EC (D1): Area 6
A5EC (D0): Areas 4 and 5
To increase memory efficiency, try to locate the same type of data at continuous locations on exact boundary addresses in order to minimize invalid areas.
Bus Operation of External Memory
The external data bus is
Table 4.13 Number of Bus Operation Cycles
Data size to | Devise | Number of bus | Remarks |
be accessed | size | operation cycles | |
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32 bits | 16 bits | 2 |
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16 bits | 16 bits | 1 |
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8 bits | 16 bits | 1 | In |
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| address (A[0]) is "0" or the #BSL signal is L. The |
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| when the LSB of the address (A[0]) is "1" or the #BSH signal is H. |
|
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| In |
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| address (A[0]) is "0" or the #BSL signal is L. The |
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| when the LSB of the address (A[0]) is "1" or the #BSH signal is H. |
32 bits | 8 bits | 4 | In |
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| bits of the data bus. In |
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| to the |
16 bits | 8 bits | 2 | In |
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| bits of the data bus. In |
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|
| connected to the |
8 bits | 8 bits | 1 | In |
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| bits of the data bus. In |
|
|
| connected to the |
These bus operations are shown in the figure below, taking the example of the A0 method. With the BSL method, the following adjustments should be made when reading the figure.
(1)For data reads, the operation is as shown in the figure below.
(2)For
(3)For
BCU
S1C33L03 FUNCTION PART | EPSON |