II CORE BLOCK: ITC (Interrupt Controller)

 

Register name

Address

Bit

Name

Function

 

Setting

 

Init.

R/W

Remarks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port input 4–7,

0040287

D7–6

–

reserved

 

 

–

 

–

–

0 when being read.

 

 

clock timer, A/D

(B)

D5

FP7

Port input 7

1

Factor is

 

0

 

No factor is

X

R/W

 

 

 

interrupt factor

 

D4

FP6

Port input 6

 

generated

 

 

 

generated

X

R/W

 

 

 

flag register

 

D3

FP5

Port input 5

 

 

 

 

 

 

X

R/W

 

 

 

 

 

D2

FP4

Port input 4

 

 

 

 

 

 

X

R/W

 

 

 

 

 

D1

FCTM

Clock timer

 

 

 

 

 

 

X

R/W

 

 

 

 

 

D0

FADE

A/D converter

 

 

 

 

 

 

X

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port input 0–3,

0040290

D7

R16TC0

16-bit timer 0 comparison A

1

IDMA

 

0

 

Interrupt

0

R/W

 

 

 

high-speed

(B)

D6

R16TU0

16-bit timer 0 comparison B

 

request

 

 

 

request

0

R/W

 

 

 

DMA Ch. 0/1,

 

D5

RHDM1

High-speed DMA Ch.1

 

 

 

 

 

 

0

R/W

 

 

 

16-bit timer 0

 

D4

RHDM0

High-speed DMA Ch.0

 

 

 

 

 

 

0

R/W

 

 

 

IDMA request

 

D3

RP3

Port input 3

 

 

 

 

 

 

0

R/W

 

 

 

register

 

D2

RP2

Port input 2

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D1

RP1

Port input 1

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D0

RP0

Port input 0

 

 

 

 

 

 

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16-bit timer 1–4

0040291

D7

R16TC4

16-bit timer 4 comparison A

1

IDMA

 

0

 

Interrupt

0

R/W

 

 

 

IDMA request

(B)

D6

R16TU4

16-bit timer 4 comparison B

 

request

 

 

 

request

0

R/W

 

 

 

register

 

D5

R16TC3

16-bit timer 3 comparison A

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D4

R16TU3

16-bit timer 3 comparison B

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D3

R16TC2

16-bit timer 2 comparison A

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D2

R16TU2

16-bit timer 2 comparison B

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D1

R16TC1

16-bit timer 1 comparison A

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D0

R16TU1

16-bit timer 1 comparison B

 

 

 

 

 

 

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16-bit timer 5,

0040292

D7

RSTX0

SIF Ch.0 transmit buffer empty

1

IDMA

 

0

 

Interrupt

0

R/W

 

 

 

8-bit timer,

(B)

D6

RSRX0

SIF Ch.0 receive buffer full

 

request

 

 

 

request

0

R/W

 

 

 

serial I/F Ch.0

 

D5

R8TU3

8-bit timer 3 underflow

 

 

 

 

 

 

0

R/W

 

 

 

IDMA request

 

D4

R8TU2

8-bit timer 2 underflow

 

 

 

 

 

 

0

R/W

 

 

 

register

 

D3

R8TU1

8-bit timer 1 underflow

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D2

R8TU0

8-bit timer 0 underflow

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D1

R16TC5

16-bit timer 5 comparison A

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D0

R16TU5

16-bit timer 5 comparison B

 

 

 

 

 

 

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial I/F Ch.1,

0040293

D7

RP7

Port input 7

1

IDMA

 

0

 

Interrupt

0

R/W

 

 

 

A/D,

(B)

D6

RP6

Port input 6

 

request

 

 

 

request

0

R/W

 

 

 

port input 4–7

 

D5

RP5

Port input 5

 

 

 

 

 

 

0

R/W

 

 

 

IDMA request

 

D4

RP4

Port input 4

 

 

 

 

 

 

0

R/W

 

 

 

register

 

D3

–

reserved

 

 

–

 

–

–

0 when being read.

 

 

 

 

D2

RADE

A/D converter

1

IDMA

 

0

 

Interrupt

0

R/W

 

 

 

 

 

D1

RSTX1

SIF Ch.1 transmit buffer empty

 

request

 

 

 

request

0

R/W

 

 

 

 

 

D0

RSRX1

SIF Ch.1 receive buffer full

 

 

 

 

 

 

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port input 0–3,

0040294

D7

DE16TC0

16-bit timer 0 comparison A

1

IDMA

 

0

 

IDMA

0

R/W

 

 

 

high-speed

(B)

D6

DE16TU0

16-bit timer 0 comparison B

 

enabled

 

 

 

disabled

0

R/W

 

 

 

DMA Ch. 0/1,

 

D5

DEHDM1

High-speed DMA Ch.1

 

 

 

 

 

 

0

R/W

 

 

 

16-bit timer 0

 

D4

DEHDM0

High-speed DMA Ch.0

 

 

 

 

 

 

0

R/W

 

 

 

IDMA enable

 

D3

DEP3

Port input 3

 

 

 

 

 

 

0

R/W

 

 

 

register

 

D2

DEP2

Port input 2

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D1

DEP1

Port input 1

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D0

DEP0

Port input 0

 

 

 

 

 

 

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16-bit timer 1–4

0040295

D7

DE16TC4

16-bit timer 4 comparison A

1

IDMA

 

0

 

IDMA

0

R/W

 

 

 

IDMA enable

(B)

D6

DE16TU4

16-bit timer 4 comparison B

 

enabled

 

 

 

disabled

0

R/W

 

 

 

register

 

D5

DE16TC3

16-bit timer 3 comparison A

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D4

DE16TU3

16-bit timer 3 comparison B

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D3

DE16TC2

16-bit timer 2 comparison A

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D2

DE16TU2

16-bit timer 2 comparison B

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D1

DE16TC1

16-bit timer 1 comparison A

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D0

DE16TU1

16-bit timer 1 comparison B

 

 

 

 

 

 

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16-bit timer 5,

0040296

D7

DESTX0

SIF Ch.0 transmit buffer empty

1

IDMA

 

0

 

IDMA

0

R/W

 

 

 

8-bit timer,

(B)

D6

DESRX0

SIF Ch.0 receive buffer full

 

enabled

 

 

 

disabled

0

R/W

 

 

 

serial I/F Ch.0

 

D5

DE8TU3

8-bit timer 3 underflow

 

 

 

 

 

 

0

R/W

 

 

 

IDMA enable

 

D4

DE8TU2

8-bit timer 2 underflow

 

 

 

 

 

 

0

R/W

 

 

 

register

 

D3

DE8TU1

8-bit timer 1 underflow

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D2

DE8TU0

8-bit timer 0 underflow

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D1

DE16TC5

16-bit timer 5 comparison A

 

 

 

 

 

 

0

R/W

 

 

 

 

 

D0

DE16TU5

16-bit timer 5 comparison B

 

 

 

 

 

 

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial I/F Ch.1,

0040297

D7

DEP7

Port input 7

1

IDMA

 

0

 

IDMA

0

R/W

 

 

 

A/D,

(B)

D6

DEP6

Port input 6

 

enabled

 

 

 

disabled

0

R/W

 

 

 

port input 4–7

 

D5

DEP5

Port input 5

 

 

 

 

 

 

0

R/W

 

 

 

IDMA enable

 

D4

DEP4

Port input 4

 

 

 

 

 

 

0

R/W

 

 

 

register

 

D3

–

reserved

 

 

–

 

–

–

0 when being read.

 

 

 

 

D2

DEADE

A/D converter

1

IDMA

 

0

 

IDMA

0

R/W

 

 

 

 

 

D1

DESTX1

SIF Ch.1 transmit buffer empty

 

enabled

 

 

 

disabled

0

R/W

 

 

 

 

 

D0

DESRX1

SIF Ch.1 receive buffer full

 

 

 

 

 

 

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A-1

B-II

ITC

S1C33L03 FUNCTION PART

EPSON

B-II-5-15