III PERIPHERAL BLOCK: SERIAL INTERFACE
•Sampling clock
In the asynchronous mode, TCLK (the clock output by the
A 1/16 division ratio is selected by writing "0" to DIVMDx , and a 1/8 ratio is selected by writing "1". Ch.0 clock division ratio selection: DIVMD0 (D4) / Serial I/F Ch.0 IrDA register (0x401E4)
Ch.1 clock division ratio selection: DIVMD1 (D4) / Serial I/F Ch.1 IrDA register (0x401E9)
Ch.2 clock division ratio selection: DIVMD2 (D4) / Serial I/F Ch.2 IrDA register (0x401F4)
Ch.3 clock division ratio selection: DIVMD3 (D4) / Serial I/F Ch.3 IrDA register (0x401F9)
Note: The DIVMDx bit becomes indeterminate at initial reset, so be sure to reset it in the software. Settings of this bit are valid only in the asynchronous mode (and when using the IrDA interface).
For receiving
SINx |
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| Start bit |
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| D0 | |||||||||||||||||||||
TCLK |
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| 8 |
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| 16 | 1 |
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| 8 |
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Sampling clock for receiving |
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| 6⋅ TCLK |
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| 10⋅ TCLK |
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| Sampling of start bit |
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| Sampling of D0 bit |
Figure 8.10 Sampling Clock for Asynchronous Receive Operation (when 1/16 division is selected)
As shown in Figure 8.10, the sampling clock is created by dividing TCLK by 16 (or 8). Its duty ratio (low: high ratio) is 6:10 (or 2:6 when divided by 8), and not 50%. Since the receive data is sampled in the middle point of each bit, the sampling clock recognizes the start bit first, and then changes the level from high to low at the second falling edge of TCLK. And at the 8th (4th for 1/8) falling edge of TCLK, it changes the level from low to high. This change in levels is repeated for the following bits of data:
Each bit of data is sampled at each rising edge of this sampling clock. When the stop bit is sampled, the sampling clock is fixed at high level until the next start bit is sampled.
If the SINx pin is returned to high level at the second falling edge of TCLK when it recognize the start bit, the data is assumed to be noise, and generation of the sampling clock is stopped.
If the SINx pin is not on a low level when the start bit is sampled at the 8th (4th for 1/8) clock, such as when the baud rate is not matched between the transmit and receive units, the serial interface stops sampling the following data and returns to a
For transmitting
TCLK
1 2 3 | . . . | 16 |
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Sampling clock for transmitting |
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| 8⋅ TCLK |
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| 8⋅ TCLK |
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Figure 8.11 Sampling Clock for Asynchronous Transmit Operation (when 1/16 division is selected)
When transmitting data, a sampling clock of a 50% duty cycle is generated from TCLK by dividing it by 16 (or 8), and each bit of data is output synchronously with this clock.
SIF
S1C33L03 FUNCTION PART | EPSON |