VII LCD CONTROLLER BLOCK: LCD CONTROLLER
Clock
The LCD controller uses the BCU clock as the source clock for its pixel clock PCLK and display memory clock MCLK. The maximum clock frequency that can be supplied to the LCD controller is 25 MHz. The BCU clock divide ratios can be set using the LCLKSEL[2:0] (D[2:0])/FIFO control register (0x39FFF4), as shown in Table 2.3 below.
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| Bus clock |
#X2SPD pin |
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| LCLKSEL[2:0] |
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CLG | BCU | 1/1 |
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| BCU_CLK | 1/2 |
| LCDC clock (PCLK, MCLK) |
CPU_CLK |
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| 1/1 or 1/2 |
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| 1/3 |
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| 1/4 |
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Figure 2.3 LCDC Clocks
Table 2.3 Selection of LCDC Clocks
LCLKSEL2 | LCLKSEL1 | LCLKSEL0 | LCDC clock |
0 | 0 | 0 | Turned off |
0 | 0 | 1 | Turned off |
0 | 1 | 0 | Turned off |
0 | 1 | 1 | Reserved (not allowed) |
1 | 0 | 0 | BCU_CLK |
1 | 0 | 1 | BCU_CLK/2 |
1 | 1 | 0 | BCU_CLK/3 |
1 | 1 | 1 | BCU_CLK/4 |
LCDC
S1C33L03 FUNCTION PART | EPSON |