II CORE BLOCK: BCU (Bus Control Unit)
Bus Cycles in External System Interface
The following shows a sample SRAM connection the basic bus cycles.
S1C33 |
| SRAM |
| S1C33 |
| SRAM |
| S1C33 |
| SRAM |
A[9:1] |
| A[8:0] |
| A[9:1] |
| A[8:0] |
| A[9:1] |
| A[8:0] |
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D[15:0] |
| I/O[15:0] |
| D[15:0] |
| I/O[15:0] |
| D[15:0] |
| I/O[15:0] |
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#RD |
| #RD |
| A0 |
| #LB |
| A0 |
| #LB |
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#WRH |
| #WRH |
| #WRH |
| #UB |
| #WRH |
| #UB |
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#WRL |
| #WRL |
| #WRL |
| #WE |
| #WRL |
| #WE |
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#CE |
| #CE |
| #CE |
| #OS |
| #CE |
| #OS |
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| #RD |
| #OE |
| #RD |
| #OE |
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(1) A0 system (little endian/big endian) |
| (2) #BSL system (little endian) |
| (3) #BSL system (big endian) | ||||||
Figure 4.18 Sample DRAM Connection
SRAM Read Cycles
Basic read cycle with no wait mode
C1
BCLK
A[23:0]addr
#CExx
D[15:0]data
#RD
#WAIT
Figure 4.19 Basic Read Cycle with No Wait
Read cycle with wait mode
Example: When the BCU has no internal wait mode and 2 wait cycles via #WAIT pin are inserted
C1 | CW | CW |
BCLK |
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A[23:0] | addr |
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#CExx |
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D[15:0] |
| data |
#RD
#WAIT
Figure 4.20 Read Cycle with Wait
The #WAIT signal is sampled at the falling edge of the transition of BCLK (bus clock) and when it is sampled on an inactive (high level), the read cycle is terminated.
Note: Insertion of wait cycles via the #WAIT pin is possible only when the device for bus conditions is set for SRAM, and SWAITE (D0) / Bus control register (0x4812E) is enabled for waiting.
BCU
S1C33L03 FUNCTION PART | EPSON |