VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
SDRBA: Number of SDRAM banks (D1) / SDRAM address configuration register (0x39FFC2)
Set the number of banks of the SDRAM.
Write "1": 4 banks
Write "0": 2 banks
Read: Valid
Set "1" when a SDRAM configured with 4 banks is used or set "0" when a SDRAM configured with 2 banks is used.
The contents set here are applied to all of areas 7, 8, 13, and 14 that are set for SDRAM.
At cold start, SDRBA is set to "0" (2 banks). At hot start, SDRBA retains its status before being initialized.
Set the CAS latency of the SDRAM.
| Table 2.17 | Setting CAS Latency | |
SDRCL1 | SDRCL0 |
| CAS latency (number of clocks) |
1 | 0 |
| 2 |
Other settings |
| Not allowed |
The SDRAM controller does not support CAS latencies other than 2.
At cold start, SDRCL is set to "11". Be sure to reset to "10" so that the CAS latency is set to 2. At hot start, SDRCL retain its status before being initialized.
Set the burst read length of the SDRAM.
Table 2.18 Setting Burst Length
SDRBL1 | SDRBL0 | Burst length (word) |
0 | 0 | 1 |
0 | 1 | 2 |
1 | 0 | 4 |
1 | 1 | 8 |
The SDRAM controller does not support burst write, so the set burst length is effective only for read cycles. At cold start, SDRBL is set to "11" (8). At hot start, SDRBL retain its status before being initialized.
Set the tRAS SDRAM parameter (ACTIVE to PRECHARGE command period).
In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM clock cycles. Specifying
Set the tRP SDRAM parameter (PRECHARGE command period).
In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM clock cycles. Specifying
Set the tRC SDRAM parameter (ACTIVE to ACTIVE command period).
In accordance with the specifications of the SDRAM, specify this parameter in terms of the number of SDRAM clock cycles. Specifying
Note: When the
SDRAM
S1C33L03 FUNCTION PART | EPSON |