
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
I/O Pins and Connection
I/O Pins
Table 2.1 lists the pins used for the SDRAM interface.
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| Table 2.1 I/O Pin List |
Pin name | I/O | Function |
A[13:12]/SDA[12:11], | O | Address bus |
A[10:1]/SDA[9:0] |
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A[15:14]/SDBA[1:0] | O | SDRAM bank select signals |
D[15:0] | I/O | Data bus |
#CE8/#RAS1/#CE14/#RAS3/#SDCE1 | O | Area 8/14 chip enable / DRAM Row strobe / SDRAM chip enable 1 |
#CE7/#RAS0/#CE13/#RAS2/#SDCE0 | O | Area 7/13 chip enable / DRAM Row strobe / SDRAM chip enable 0 |
#HCAS/#SDCAS | O | DRAM column address strobe |
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| strobe |
#LCAS/#SDRAS | O | DRAM column address strobe |
BCLK/SDCLK | O | Bus clock output / SDRAM operating clock |
P20/#DRD/SDCKE | I/O | I/O port / DRAM read / SDRAM clock enable |
P21/#DWE/#GAAS/#SDWE | I/O | I/O port / DRAM write |
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| SDRAM write |
P33/#DMAACK1/SIN3/SDA10 | I/O | I/O port / HSDMA Ch. 1 acknowledge output / Serial I/F Ch. 3 data input / |
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| SDRAM address bus 10 |
P32/#DMAACK0/#SRDY3/HDQM | I/O | I/O port / HSDMA Ch. 0 acknowledge output / Serial I/F Ch. 3 ready signal |
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| output / SDRAM data |
P15/EXCL4/#DMAEND0/#SCLK3/ | I/O | I/O port / |
LDQM |
| signal output / Serial I/F Ch. 3 clock input/output / SDRAM data |
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| input/output mask signal output |
Connection Examples
Figures 2.2 and 2.3 show examples of how to connect
S1C33 |
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| 256M SDRAM |
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| (4M x 16 bits x 4 banks) |
SDA[12:11](A[13:12]) |
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| A[12:11] |
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SDA10(P33) |
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| A10 |
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SDA[9:0](A[10:1]) |
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| A[9:0] |
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SDBA[1:0](A[15:14]) |
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| BA[1:0] |
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D[15:0] |
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| DQ[15:0] |
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BCLK |
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| CLK |
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SDCKE(P20) |
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| CKE |
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#SDCE0/1(#CE7/8) |
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| #CS |
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#SDCAS(#HCAS) |
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| #CAS |
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#SDRAS(#LCAS) |
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| #RAS |
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#SDWE(P21) |
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| #WE |
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HDQM(P32) |
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| DQMU |
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LDQM(P15) |
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| DQML |
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Figure 2.2 Connecting a
EPSON | S1C33L03 FUNCTION PART |