VII LCD CONTROLLER BLOCK: LCD CONTROLLER

A-1

VII-2 LCD CONTROLLER

This section describes the functions and control procedures of the LCD controller. For details on setting the external display memory bus conditions and parameters, refer to Section II-4, "BCU (Bus Control Unit)", and Section VI-2, "SDRAM Interface".

Overview

Features

The features of the LCD controller (LCDC) are described below.

S1C33 core CPU interface

•The control registers are mapped into the area-6 addresses 0x39FFE0 to 0x39FFFF (an internal #WAIT signal is used).

•A dedicated DMA controller is built-in for the transferal of display data.

Compatible display types

•4- or 8-bit monochrome LCD panel

•4- or 8-bit color LCD panel

•Single-drive passive display, single panel

•Typical resolutions

640 ⋅

480 (1-bpp mode)

* bpp = bits per pixel

640 ⋅

240 (2-bpp mode)

 

320 ⋅

240 (4-bpp mode)

 

240 ⋅

160 (8-bpp mode)

 

Display modes

•Portrait display (display screen rotated 90 degrees) is supported in the hardware.

•Due to frame rate modulation, grayscale display is possible in up to 16 shades of gray when a monochrome

passive LCD panel is used.

1-bpp mode: Two-shade display using a 2 ⋅ 4-bit look-up table

2-bpp mode: Four-shade display using a 4 ⋅ 4-bit look-up table

4-bpp mode: 16-shade display using a 16 ⋅ 4-bit look-up table

•Of 4,096 colors, a maximum of 256 colors can be simultaneously displayed on a color passive LCD panel.

1-bpp mode: Two-color display using three 2 ⋅ 4-bit look-up tables

2-bpp mode: Four-color display using three 4 ⋅ 4-bit look-up tables

4-bpp mode: 16-color display using three 16 ⋅ 4-bit look-up tables

8-bpp mode: 256-color display using a 20 ⋅ 4-bit look-up table

•Two images can be simultaneously displayed on split screens of the LCD panel (landscape display mode).

•Virtual display (Images larger than the actual panel size can be displayed by panning or scrolling the screen.)

Display frame buffer

•A maximum of 256K bytes in memory connected to areas 7/8 or areas 13/14 can be used as a display frame buffer.

•SDRAM is also supported by the 16 ⋅ 16-bit FIFO.

Clock

•The PCLK (pixel clock) and MCLK (memory clock) for the LCD controller can be selected from among four clock frequencies derived from the BCU clock by dividing the BCU clock by 1, 2, 3, or 4.

•PCLK and MCLK frequencies: Maximum of 25 MHz

B-VII

LCDC

S1C33L03 FUNCTION PART

EPSON

B-VII-2-1