I OUTLINE: LIST OF PINS
Table 3.4 List of Pins for LCD Controller
Pin name | Pin No. | I/O |
| Function | |
FPDAT[7:4] | O | – | 4 | ||
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| Data bus for | |
FPDAT[3:0] | O | – | FPDAT[3:0]: | 4 | |
GPO[6:3] |
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| GPO[6:3]: | |
FPFRAME | 23 | O | – | Frame pulse output | |
FPLINE | 24 | O | – | Line pulse output | |
FPSHIFT | 25 | O | – | Shift clock output | |
DRDY(MOD) | 22 | O | – | MOD: | LCD backplane bias (for panels other than |
(FPSHIFT2) |
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| FPSHIFT2: | Second shift clock (for |
LCDPWR | 26 | O | – | LCD power control output (active high) |
Table 3.5 List of Pins for Clock Generator
Pin name | Pin No. | I/O |
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| Function |
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OSC1 | 68 | I | – | ||||||
OSC2 | 67 | O | – |
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OSC3 | 129 | I | – | ||||||
OSC4 | 128 | O | – |
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PLLS[1:0] | 112,113 | I | – | PLL |
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| PLLS1 | PLLS0 | fin (fOSC3) | fout (fPSCIN) |
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| 1 | 1 |
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| 0 | 1 |
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| 0 | 0 | PLL is not used | L | ||
PLLC | 115 | – | – | Capacitor connecting pin for PLL |
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| Table 3.6 List of Other Pins | |
Pin name | Pin No. | I/O | Function | ||
/down | |||||
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ICEMD | 125 | I | Pull- | ||
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| down | When this pin is set to High, all the output pins go into | |
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| it possible to disable the S1C33 chip on the board. | |
DSIO | 117 | I/O | Serial I/O pin for debugging | ||
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| This pin is used to communicate with the debugging tool S5U1C33000H. | |
#X2SPD | 140 | I | – | Clock doubling mode | |
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| 1: CPU clock = bus clock ⋅ 1, 0: CPU clock = bus clock ⋅ 2 | |
#NMI | 130 | I | NMI request input pin | ||
#RESET | 69 | I | Initial reset input pin |
Note: "#" in the pin names indicates that the signal is low active.
Pin
S1C33L03 FUNCTION PART | EPSON |