
III PERIPHERAL BLOCK:
III-3 8-BIT PROGRAMMABLE TIMERS
Configuration of
The Peripheral Block contains six channels of
Figure 3.1 shows the structure of the
Clock
Prescaler
generator
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Clock output |
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| Underflow |
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Underflow signal output |
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Underflow Interrupt
interrupt controller
Data bus | ||
Data buffer (PTDx) | ||
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Control registers |
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Figure 3.1 Structure of
Each timer consists of an
Output Pins of
The underflow signals of
Table 3.1 shows the pins that are used to output the underflow signals of the
Table 3.1 Output Pins of
Pin name | I/O | Function | Function select bit |
P10/EXCL0/ | I/O | I/O port / | CFP10(D0)/P1 function select register (0x402D4) |
T8UF0 |
| input / | CFEX1(D1)/Port function extension register (0x402DF) |
P11/EXCL1/ | I/O | I/O port / | CFP11(D1/P1 function select register (0x402D4) |
T8UF1 |
| input / | CFEX1(D1)/Port function extension register (0x402DF) |
P12/EXCL2/ | I/O | I/O port / | CFP12(D2/P1 function select register (0x402D4) |
T8UF2 |
| input / | CFEX0(D0)/Port function extension register (0x402DF) |
P13/EXCL3/ | I/O | I/O port / | CFP13(D3/P1 function select register (0x402D4) |
T8UF3 |
| input / | CFEX1(D1)/Port function extension register (0x402DF) |
T8UFx (output pin of the
This pin outputs a clock divided in each
How to set the output pins of the
All pins used by the
Then, after setting the above, write "1" to the I/O port's I/O control bit IOC1x (D[3:0]) / P1 I/O control register (0x402D6) to set to output mode. In input mode, the pin functions as the
8TM
S1C33L03 FUNCTION PART | EPSON |