4 PERIPHERAL CIRCUITS
Register name | Address | Bit | Name | Function |
|
|
|
| Setting | Init. | R/W | Remarks | ||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0048258 | DF | D3ADRL15 | D) Ch.3 destination address[15:0] |
|
|
|
|
|
|
|
|
| X | R/W |
| |
DMA Ch.3 | (HW) | DE | D3ADRL14 | S) Invalid |
|
|
|
|
|
|
|
|
| X |
|
|
| DD | D3ADRL13 |
|
|
|
|
|
|
|
|
|
| X |
|
| |
destination |
| DC | D3ADRL12 |
|
|
|
|
|
|
|
|
|
| X |
|
|
address |
| DB | D3ADRL11 |
|
|
|
|
|
|
|
|
|
| X |
|
|
register |
| DA | D3ADRL10 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D9 | D3ADRL9 |
|
|
|
|
|
|
|
|
|
| X |
|
|
Note: |
| D8 | D3ADRL8 |
|
|
|
|
|
|
|
|
|
| X |
|
|
D) Dual address |
| D7 | D3ADRL7 |
|
|
|
|
|
|
|
|
|
| X |
|
|
mode |
|
|
|
|
|
|
|
|
|
|
|
|
| |||
| D6 | D3ADRL6 |
|
|
|
|
|
|
|
|
|
| X |
|
| |
S) Single |
|
|
|
|
|
|
|
|
|
|
|
|
| |||
| D5 | D3ADRL5 |
|
|
|
|
|
|
|
|
|
| X |
|
| |
address |
|
|
|
|
|
|
|
|
|
|
|
|
| |||
| D4 | D3ADRL4 |
|
|
|
|
|
|
|
|
|
| X |
|
| |
mode |
|
|
|
|
|
|
|
|
|
|
|
|
| |||
|
| D3 | D3ADRL3 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D2 | D3ADRL2 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D1 | D3ADRL1 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D0 | D3ADRL0 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||
004825A | DF | D3MOD1 | Ch.3 transfer mode | D3MOD[1:0] |
|
|
| Mode | 0 | R/W |
| |||||
DMA Ch.3 | (HW) | DE | D3MOD0 |
|
| 1 |
| 1 |
|
|
| Invalid | 0 |
|
| |
|
|
|
|
| 1 |
| 0 |
|
|
| Block |
|
|
| ||
destination |
|
|
|
|
| 0 |
| 1 |
| Successive |
|
|
| |||
address |
|
|
|
|
| 0 |
| 0 |
|
|
| Single |
|
|
| |
register |
| DD | D3IN1 | D) Ch.3 destination address | D3IN[1:0] |
|
| Inc/dec | 0 | R/W |
| |||||
|
| DC | D3IN0 | control |
| 1 |
| 1 |
| Inc.(no init) | 0 |
|
| |||
Note: |
|
|
| S) Invalid |
| 1 |
| 0 |
|
| Inc.(init) |
|
|
| ||
D) Dual address |
|
|
|
|
| 0 |
| 1 |
| Dec.(no init) |
|
|
| |||
mode |
|
|
|
|
|
|
|
|
|
| ||||||
|
|
|
|
| 0 |
| 0 |
|
|
| Fixed |
|
|
| ||
S) Single |
|
|
|
|
|
|
|
|
|
|
|
| ||||
| DB | D3ADRH11 | D) Ch.3 destination |
|
|
|
|
|
|
|
|
| X | R/W |
| |
address |
|
|
|
|
|
|
|
|
|
|
| |||||
| DA | D3ADRH10 | address[27:16] |
|
|
|
|
|
|
|
|
| X |
|
| |
mode |
|
|
|
|
|
|
|
|
|
|
|
| ||||
|
| D9 | D3ADRH9 | S) Invalid |
|
|
|
|
|
|
|
|
| X |
|
|
|
| D8 | D3ADRH8 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D7 | D3ADRH7 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D6 | D3ADRH6 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D5 | D3ADRH5 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D4 | D3ADRH4 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D3 | D3ADRH3 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D2 | D3ADRH2 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D1 | D3ADRH1 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D0 | D3ADRH0 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
004825C | – | reserved |
|
|
|
|
| – |
|
| – | – | Undefined in read. | |||
DMA Ch.3 | (HW) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
enable register |
| D0 | HS3_EN | Ch.3 enable | 1 |
| Enable |
| 0 |
| Disable | 0 | R/W |
| ||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
004825E | – | reserved |
|
|
|
|
| – |
|
| – | – | Undefined in read. | |||
DMA Ch.3 | (HW) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
trigger flag |
| D0 | HS3_TF | Ch.3 trigger flag clear (writing) | 1 |
| Clear |
|
| 0 |
| No operation | 0 | R/W |
| |
register |
|
|
| Ch.3 trigger flag status (reading) | 1 |
| Set |
|
| 0 |
| Cleared |
|
|
|
EPSON | S1C33L03 PRODUCT PART |