V DMA BLOCK: HSDMA (High-Speed DMA)

Operation in Single-Address Mode

The operation of each transfer mode is almost the same as that of dual-address mode (see the previous section). However, data read/write operation is performed simultaneously in single-address mode.

The following explains the data transfer operation different from dual-address mode.

#DMAACKx signal output and bus operation

When the HSDMA circuit accepts the DMA request, it outputs a low-level pulse from the #DMAACKx pin and starts bus operation for the memory at the same time.

The contents of this bus operation are as follows:

•Data transfer from I/O device to memory

The address that has been set in the memory address register is output to the address bus.

A write operation is performed under the interface conditions set on the area to which the memory at the destination of transfer belongs. The data bus is left floating.

The external I/O device outputs the transfer data onto the data bus using the #DMAACKx signal as the read signal. The memory takes in this data using the write signal.

•Data transfer from memory to an I/O device

The address that has been set in the memory address register is output to the address bus.

A read operation is performed under the interface conditions set on the area to which the memory at the source of transfer belongs.

The memory outputs the transfer data onto the data bus using the read signal.

The external I/O device takes in the data from the data bus using the #DMAACKx signal as the write signal.

If the transfer data size is 16 bits and the I/O device is an 8-bit device, two bus operations are performed. Otherwise, transfer is completed in one bus operation.

#DMAENDx signal output

When the transfer counter reaches 0, the end-of-transfer signal is output from the #DMAENDx pin indicating that a specified number of transfers has been completed. At the same time, the interrupt factor for the completion of HSDMA is generated.

B-V-2-12

EPSON

S1C33L03 FUNCTION PART