4 PERIPHERAL CIRCUITS
Register name | Address | Bit | Name | Function |
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| Setting | Init. | R/W | Remarks | ||||
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0048230 | DF | TC1_L7 | Ch.1 transfer counter[7:0] |
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| X | R/W |
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DMA Ch.1 | (HW) | DE | TC1_L6 | (block transfer mode) |
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| X |
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transfer |
| DD | TC1_L5 |
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| X |
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counter |
| DC | TC1_L4 | Ch.1 transfer counter[15:8] |
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| X |
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register |
| DB | TC1_L3 | (single/successive transfer mode) |
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| X |
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| DA | TC1_L2 |
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| X |
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| D9 | TC1_L1 |
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| X |
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| D8 | TC1_L0 |
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| X |
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| D7 | BLKLEN17 | Ch.1 block length |
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| X | R/W |
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| D6 | BLKLEN16 | (block transfer mode) |
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| X |
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| D5 | BLKLEN15 |
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| X |
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| D4 | BLKLEN14 | Ch.1 transfer counter[7:0] |
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| X |
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| D3 | BLKLEN13 | (single/successive transfer mode) |
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| X |
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| D2 | BLKLEN12 |
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| X |
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| D1 | BLKLEN11 |
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| X |
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| D0 | BLKLEN10 |
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| X |
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0048232 | DF | DUALM1 | Ch.1 address mode selection | 1 |
| Dual addr | 0 |
| Single addr | 0 | R/W |
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DMA Ch.1 | (HW) | DE | D1DIR | D) Invalid |
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| – |
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| – | – |
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control register |
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| S) Ch.1 transfer direction control | 1 |
| Memory WR | 0 |
| Memory RD | 0 | R/W |
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| – | reserved |
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| – |
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| – | – | Undefined in read. | |
Note: |
| D7 | TC1_H7 | Ch.1 transfer counter[15:8] |
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| X | R/W |
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D) Dual address |
| D6 | TC1_H6 | (block transfer mode) |
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| X |
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mode |
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| D5 | TC1_H5 |
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| X |
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S) Single |
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| D4 | TC1_H4 | Ch.1 transfer counter[23:16] |
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| X |
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address |
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| D3 | TC1_H3 | (single/successive transfer mode) |
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| X |
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mode |
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| D2 | TC1_H2 |
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| X |
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| D1 | TC1_H1 |
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| X |
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| D0 | TC1_H0 |
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| X |
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0048234 | DF | S1ADRL15 | D) Ch.1 source address[15:0] |
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| X | R/W |
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DMA Ch.1 | (HW) | DE | S1ADRL14 | S) Ch.1 memory address[15:0] |
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| X |
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| DD | S1ADRL13 |
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| X |
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source address |
| DC | S1ADRL12 |
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| X |
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| DB | S1ADRL11 |
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| X |
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| DA | S1ADRL10 |
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| X |
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Note: |
| D9 | S1ADRL9 |
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| X |
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D) Dual address |
| D8 | S1ADRL8 |
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| X |
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mode |
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| D7 | S1ADRL7 |
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| X |
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S) Single |
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| D6 | S1ADRL6 |
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| X |
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address |
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| D5 | S1ADRL5 |
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| X |
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mode |
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| D4 | S1ADRL4 |
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| X |
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| D3 | S1ADRL3 |
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| X |
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| D2 | S1ADRL2 |
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| X |
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| D1 | S1ADRL1 |
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| X |
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| D0 | S1ADRL0 |
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| X |
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0048236 | DF | – | reserved |
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| – |
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| – | – |
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DMA Ch.1 | (HW) | DE | DATSIZE1 | Ch.1 transfer data size | 1 |
| Half word | 0 |
| Byte | 0 | R/W |
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| DD | S1IN1 | D) Ch.1 source address control | S1IN[1:0] |
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| Inc/dec | 0 | R/W |
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source address |
| DC | S1IN0 | S) Ch.1 memory address control |
| 1 | 1 |
| Inc.(no init) | 0 |
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| 1 | 0 |
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| Inc.(init) |
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| 0 | 1 |
| Dec.(no init) |
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Note: |
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| 0 | 0 |
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| Fixed |
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D) Dual address |
| DB | S1ADRH11 | D) Ch.1 source address[27:16] |
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| X | R/W |
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mode |
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| DA | S1ADRH10 | S) Ch.1 memory address[27:16] |
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| X |
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S) Single |
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| D9 | S1ADRH9 |
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| X |
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address |
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| D8 | S1ADRH8 |
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| X |
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mode |
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| D7 | S1ADRH7 |
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| X |
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| D6 | S1ADRH6 |
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| X |
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| D5 | S1ADRH5 |
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| X |
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| D4 | S1ADRH4 |
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| X |
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| D3 | S1ADRH3 |
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| X |
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| D2 | S1ADRH2 |
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| X |
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| D1 | S1ADRH1 |
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| X |
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| D0 | S1ADRH0 |
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| X |
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S1C33L03 PRODUCT PART | EPSON |