III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS
TC015–TC00: Timer 0 counter data (D[F:0]) / 16-bit timer 0 counter data register (0x48184)
TC115–TC10: Timer 1 counter data (D[F:0]) / 16-bit timer 1 counter data register (0x4818C)
TC215–TC20: Timer 2 counter data (D[F:0]) / 16-bit timer 2 counter data register (0x48194)
TC315–TC30: Timer 3 counter data (D[F:0]) / 16-bit timer 3 counter data register (0x4819C)
TC415–TC40: Timer 4 counter data (D[F:0]) / 16-bit timer 4 counter data register (0x481A4)
TC515–TC50: Timer 5 counter data (D[F:0]) / 16-bit timer 5 counter data register (0x481AC)
The counter data of each timer can be read from this register.
The data can be read out at any time.
Since TCx is a read-only register, writing to this register is ignored.
At initial reset, TCx is not initialized.
P16T02–P16T00: Timer 0 interrupt level (D[2:0]) / 16-bit timer 0/1 interrupt priority register (0x40266)
P16T12–P16T10: Timer 1 interrupt level (D[6:4]) / 16-bit timer 0/1 interrupt priority register (0x40266)
P16T22–P16T20: Timer 2 interrupt level (D[2:0]) / 16-bit timer 2/3 interrupt priority register (0x40267)
P16T32–P16T30: Timer 3 interrupt level (D[6:4]) / 16-bit timer 2/3 interrupt priority register (0x40267)
P16T42–P16T40: Timer 4 interrupt level (D[2:0]) / 16-bit timer 4/5 interrupt priority register (0x40268)
P16T52–P16T50: Timer 5 interrupt level (D[6:4]) / 16-bit timer 4/5 interrupt priority register (0x40268)
Sets the priority levels of 16-bit programmable timer interrupts.
The priority level can be set in the range of 0 to 7.
At initial reset, P16Tx becomes indeterminate.
E16TU0, E16TC0: Timer 0 interrupt enable (D2, D3) / 16-bit timer 0/1 interrupt enable register (0x40272)
E16TU1, E16TC1: Timer 1 interrupt enable (D6, D7) / 16-bit timer 0/1 interrupt enable register (0x40272)
E16TU2, E16TC2: Timer 2 interrupt enable (D2, D3) / 16-bit timer 2/3 interrupt enable register (0x40273)
E16TU3, E16TC3: Timer 3 interrupt enable (D6, D7) / 16-bit timer 2/3 interrupt enable register (0x40273)
E16TU4, E16TC4: Timer 4 interrupt enable (D2, D3) / 16-bit timer 4/5 interrupt enable register (0x40274)
E16TU5, E16TC5: Timer 5 interrupt enable (D6, D7) / 16-bit timer 4/5 interrupt enable register (0x40274)
Enables or disables the generation of an interrupt to the CPU.
Write "1": Interrupt enabled
Write "0": Interrupt disabled
Read: Valid
The E16TUx and E16TCx are provided for the comparison B and comparison A interrupt factors, respectively. The interrupt for which the bit is set to "1" is enabled, and the interrupt for which the bit is set to "0" is disabled.
At initial reset, these bits are set to "0" (interrupt disabled).
F16TU0, F16TC0: Timer 0 interrupt factor flag (D2, D3) / 16-bit timer 0/1 interrupt factor flag register (0x40282)
F16TU1, F16TC1: Timer 1 interrupt factor flag (D6, D7) / 16-bit timer 0/1 interrupt factor flag register (0x40282)
F16TU2, F16TC2: Timer 2 interrupt factor flag (D2, D3) / 16-bit timer 2/3 interrupt factor flag register (0x40283)
F16TU3, F16TC3: Timer 3 interrupt factor flag (D6, D7) / 16-bit timer 2/3 interrupt factor flag register (0x40283)
F16TU4, F16TC4: Timer 4 interrupt factor flag (D2, D3) / 16-bit timer 4/5 interrupt factor flag register (0x40284)
F16TU5, F16TC5: Timer 5 interrupt factor flag (D6, D7) / 16-bit timer 4/5 interrupt factor flag register (0x40284)
Indicates the status of 16-bit programmable timer interrupt generation.
When read
Read "1": Interrupt factor has occurred
Read "0": No interrupt factor has occurred
When written using the reset-only method (default)
Write "1": Interrupt factor flag is reset
Write "0": Invalid
When written using the read/write method
Write "1": Interrupt flag is set
Write "0": Interrupt flag is reset
