1 OUTLINE

Pin name

Pin No.

I/O

Pull-up

 

Function

P26

6

I/O

–

P26:

I/O port when CFP26(D6/0x402D8) = "0" (default)

TM4

 

 

 

TM4:

16-bit timer 4 output when CFP26(D6/0x402D8) = "1"

SOUT2

 

 

 

SOUT2:

Serial I/F Ch. 2 data output when SSOUT2(D1/0x402DB) = "1" and

 

 

 

 

 

CFP26(D6/0x402D8) = "0"

P27

7

I/O

–

P27:

I/O port when CFP27(D7/0x402D8) = "0" (default)

TM5

 

 

 

TM5:

16-bit timer 5 output when CFP27(D7/0x402D8) = "1"

SIN2

 

 

 

SIN2:

Serial I/F Ch. 2 data input when SSIN2(D0/0x402DB) = "1" and

 

 

 

 

 

CFP27(D7/0x402D8) = "0"

P30

75

I/O

–

P30:

I/O port when CFP30(D0/0x402DC) = "0" (default)

#WAIT

 

 

 

#WAIT:

Wait cycle request input when CFP30(D0/0x402DC) = "1"

#CE4&5

 

 

 

#CE4&5:

Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1" and

 

 

 

 

 

IOC30(D0/0x402DE) = "1"

P31

74

I/O

–

P31:

I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0"

#BUSGET

 

 

 

 

(default)

#GARD

 

 

 

#BUSGET:

Bus status monitor signal output for bus release request when

GPIO2

 

 

 

 

CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0"

 

 

 

 

#GARD:

Area read signal output for GA when CFEX3(D3/0x402DF) = "1"

 

 

 

 

GPIO2:

LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and

 

 

 

 

 

BREQEN(D2/0x39FFFD) = "0"

P32

73

I/O

–

P32:

I/O port when CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1)

#DMAACK0

 

 

 

 

= "0" (default)

#SRDY3

 

 

 

#DMAACK0:

HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1" and

HDQM

 

 

 

 

SDRENA(D7/0x39FFC1) = "0"

 

 

 

 

#SRDY3:

Serial I/F Ch. 3 ready signal input/output when SSRDY3(D3/0x402D7) =

 

 

 

 

 

"1", CFP32(D2/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"

 

 

 

 

HDQM:

SDRAM data (high byte) input/output mask signal when

 

 

 

 

 

SDRENA(D7/0x39FFC1) = "1"

P33

72

I/O

–

P33:

I/O port when CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1)

#DMAACK1

 

 

 

 

= "0" (default)

SIN3

 

 

 

#DMAACK1:

HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1" and

SDA10

 

 

 

 

SDRENA(D7/0x39FFC1) = "0"

 

 

 

 

SIN3:

Serial I/F Ch. 3 data input when SSIN3(D0/0x402D7) = "1",

 

 

 

 

 

CFP33(D3/0x402DC) = "0" and SDRENA(D7/0x39FFC1) = "0"

 

 

 

 

SDA10:

SDRAM address bus bit 10 when SDRENA(D7/0x39FFC1) = "1"

P34

71

I/O

–

P34:

I/O port when CFP34(D4/0x402DC) = "0" (default)

#BUSREQ

 

 

 

#BUSREQ:

Bus release request input when CFP34(D4/0x402DC) = "1"

#CE6

 

 

 

#CE6:

Area 6 chip enable when CFP34(D4/0x402DC) = "1" and

GPIO0

 

 

 

 

IOC34(D4/0x402DE) = "1"

 

 

 

 

GPIO0:

LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and

 

 

 

 

 

BREQEN(D2/0x39FFFD) = "0"

P35

70

I/O

–

P35:

I/O port when CFP35(D5/0x402DC) = "0" (default)

#BUSACK

 

 

 

#BUSACK:

Bus acknowledge output when CFP35(D5/0x402DC) = "1" and

GPIO1

 

 

 

 

CFP34(D4/0x402DC) = "1"

 

 

 

 

GPIO1:

LCDC general-purpose I/O when LCDCEN(D5/0x39FFE3) = "1" and

 

 

 

 

 

BREQEN(D2/0x39FFFD) = "0"

A-10

EPSON

S1C33L03 PRODUCT PART